LM5117PMH/NOPB National Semiconductor, LM5117PMH/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM5117PMH/NOPB
• Description: IC BUCK CONTROLLER 20-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LM5117PMH/NOPB

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 530kHz
• Duty Cycle: 95%
• Voltage - Supply: 5.5 V ~ 65 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Ramp Generator and Emulated
Current Sense
The ramp signal used in the pulse width modulator for tradi-
tional current mode control is typically derived directly from
the high-side switch current. This switch current corresponds
to the positive slope portion of the inductor current. Using this
signal for the PWM ramp simplifies the control loop transfer
function to a single pole response and provides inherent input
voltage feed-forward compensation.
The disadvantage of using the high-side switch current signal
for PWM control is the large leading edge spike due to circuit
parasitics that must be filtered or blanked. Minimum achiev-
able pulse width is limited by the filtering, blanking time and
propagation delay with a high-side current sensing scheme.
In the applications where the input voltage may be relatively
large in comparison to the output voltage, controlling small
pulse widths and duty cycles are necessary for regulation.
The LM5117 utilizes a unique ramp generator which does not
actually measure the high-side switch current but rather re-
constructs the signal. Representing or emulating the inductor
current provides a ramp signal to the PWM comparator that
is free of leading edge spikes and measurement or filtering
delays, while maintaining the advantages of traditional peak
current mode control.
The current reconstruction is comprised of two elements: a
sample-and-hold DC level and the emulated inductor current
ramp as shown in
derived from a measurement of the recirculating current flow-
ing through the current sense resistor. The voltage across the
sense resistor is sampled and held just prior to the onset of
the next conduction interval of the high-side switch. The cur-
rent sense amplifier with a gain of 10 and sample-and-hold
circuit provide the DC level of the reconstructed current signal
as shown in
FIGURE 7. Composition of Emulated Current Sense
Figure
Figure
8.
7. The sample-and-hold DC level is
Signal
30143216
14
The positive slope inductor current ramp is emulated by
C
nected between SW and RAMP. R
nected to VIN directly because the RAMP pin absolute
maximum voltage rating could be exceeded under high input
voltage conditions. C
during the off-time and must be fully discharged during the
minimum off-time. This limits the ramp capacitor to be less
than 2nF. A good quality, thermally stable ceramic capacitor
is recommended for C
The selection of R
ing a K factor, which is defined as:
Where A
10. By choosing 1 as the K factor, the regulator removes any
error after one switching cycle and the design procedure is
simplified. See Application Information for detailed informa-
tion.
Error Amplifier and PWM
Comparator
The internal high-gain error amplifier generates an error sig-
nal proportional to the difference between the FB pin voltage
and the internal precision 0.8V reference. The output of error
amplifier is connected to the COMP pin allowing the user to
provide Type 2 loop compensation components, R
C
FIGURE 8. RAMP Generator and Current Limit Circuit
RAMP
COMP
FIGURE 9. Feedback Configuration and PWM
connected between RAMP and AGND and R
and optional C
S
is the current sense amplifier gain which is normally
RAMP
RAMP
HF
RAMP
and C
Comparator
.
is discharged by an internal switch
.
RAMP
can be simplified by adopt-
RAMP
should not be con-
30143213
RAMP
COMP
30143217
con-
(4)
,