BD9140MUV-E2 Rohm Semiconductor, BD9140MUV-E2 Datasheet - Page 8

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BD9140MUV-E2

Manufacturer Part Number
BD9140MUV-E2
Description
IC SWITCH REG 2A W/FET VQFN020
Manufacturer
Rohm Semiconductor
Series
-r
Type
Step-Down (Buck), PWM - Current Moder
Datasheet

Specifications of BD9140MUV-E2

Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
2.5 V ~ 6 V
Current - Output
2A
Frequency - Switching
500kHz
Voltage - Input
4.5 V ~ 13.2 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
●Switching regulator efficiency
●Consideration on permissible dissipation and heat generation
© 2009 ROHM Co., Ltd. All rights reserved.
BD9141MUV
www.rohm.com
η=
Efficiency ŋ may be expressed by the equation shown below:
Efficiency may be improved by reducing the switching regulator power dissipation factors P
Dissipation factors:
1) ON resistance dissipation of inductor and FET:PD(I
2) Gate charge/discharge dissipation:PD(Gate)
3) Switching dissipation:PD(SW)
4) ESR dissipation of capacitor:PD(ESR)
5) Operating current dissipation of IC:PD(IC)
1)PD(I
current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]:Gate capacitance of FET, f[H]:Switching frequency, V[V]:Gate driving voltage of FET)
3)PD(SW)=
4)PD(ESR)=I
5)PD(IC)=Vin×I
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
As R
consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
V
3.0
2.0
1.0
4.0
ONP
OUT
0
Vin×Iin
2
R)=I
0
①3.56W
②2.21W
③0.70W
④0.34W
×I
is greater than R
OUT
OUT
25
RMS
Ambient temperature:Ta [℃]
If V
Vin
2
×(R
CC
2
CC
×100[%]=
2
×C
I
×ESR (I
50
Fig.26 Thermal derating curve
OUT
=8V, V
COIL
(I
RSS
I
DRIVE
=2A, for example,
CC
R
P=2
75
+R
① 4 layers (Copper foil area : 5505mm
② 4 layers (Copper foil area : 10.29m
③ 4 layers (Copper foil area : 10.29m
④ IC only.
(VQFN020V4040)
ON
×I
[A]:Circuit current.)
D=V
OUT
ONN
copper foil in each layers.
θj-a=35.1℃/W
copper foil in each layers.
θj-a=56.6℃/W
θj-a=178.6℃/W
θj-a=367.6℃/W
2
ON
=0.09375+0.03
=0.12375[Ω]
=0.625×0.15+(1-0.625)×0.08
OUT
100
×0.12375=0.495[W]
RMS
P
=5V, R
OUT
) (R
Pin
in this IC, the dissipation increases as the ON duty becomes greater. With the
OUT
105
×f
[A]:Ripple current of capacitor, ESR[Ω]:Equivalent series resistance.)
/V
125
COIL
CC
×100[%]=
ONP
(C
=5/8=0.625
[Ω]:DC resistance of inductor, R
RSS
=0.15Ω, R
150
[F]:Reverse transfer capacitance of FET, I
2
2
)
)
2
)
P
ONN
OUT
P
OUT
=0.08Ω
+P
2
R)
8/15
D
α
P=I
R
D:ON duty (=V
R
R
R
I
OUT
ON
COIL
ONP
ONN
×100[%]
OUT
=D×R
:Output current
:ON resistance of P-channel MOS FET
:ON resistance of N-channel MOS FET
:DC resistance of coil
2
×R
ONP
ON
ON
[Ω]:ON resistance of FET, I
+(1-D)R
OUT
/V
CC
ONN
)
DRIVE
D
α as follows:
[A]:Peak current of gate.)
Technical Note
2009.09 - Rev.B
OUT
[A]:Output

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