DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 28

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
RSYNC10
RSYNC11
RSYNC12
RSYNC13
RSYNC14
RSYNC15
RSYNC16
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
RSYNC9
TVSYNC
RVDATA
TVDATA
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RCLK9
TVCLK
TVDEN
RVCLK
NAME
PACKAGE PINS
256
M2
M1
M4
M5
M7
G7
G1
H4
N2
R3
H7
G2
H1
G3
H3
N5
R2
R7
N6
E1
F4
L5
T1
T4
F1
L2
K4
L3
P1
P3
T3
F2
F3
J1
J5
J4
J3
J2
VOICE INTERFACE IO PINS - DS33W41 AND DS33W11 ONLY
144
G1
J1
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TYPE
O
I
I
I
I
I
I
I
Serial Interface Receive Clock Input (RCLK[1:16]). Reference clock for
receive serial data on RDATA. Gapped clocking is supported, up to the
maximum RCLK frequency of 52MHz.
Not all serial port signals are available on all products in the device family.
Unused input pins should be tied to VSS.
DS33X41/X42/W41/W11: RCLK5 – RCLK16 not used.
DS33X81/X82: RCLK9 – RCLK16 not used.
Receive Frame/Multiframe Synchronization Input (RSYNC[1:16]).
Receive Sync that indicates frame boundaries or multiframe boundaries
for T1/E1/T3/E3 signals present on RDATA. It must be a multiframe sync
for VCAT applications.
Not all serial port signals are available on all products in the device family.
Unused input pins should be tied to VSS.
DS33X41/X42/W41/W11: RSYNC5 – RSYNC16 not used.
DS33X81/X82: RSYNC9 – RSYNC16 not used.
Transmit Voice Data Input. Input voice data stream containing multiple
DS0s. Referenced to TVCLK. Disabled when TVDEN is high. This signal
is only available on the DS33W41 and DS33W11.
Transmit Voice Clock Input. Input clock that times TVDATA. May be
gapped. Maximum clock speed 52MHz. This signal is only available on
the DS33W41 and DS33W11.
Transmit Voice Synchronization Input. Input signal that indicates frame
boundaries on voice data stream (TVDATA), sampled by TVCLK,
frequency of 8 kHz. This signal is only available on the DS33W41 and
DS33W11.
Transmit Voice Data Enable. May be used in place of a gapped TVCLK.
If low, TVDATA is valid. If a gapped TVCLK is used and this signal is not
used, tie this input low. This signal is only available on the DS33W41 and
DS33W11.
Receive Voice Data Output. Outputs voice data stream from internal
FIFO using RVCLK. Maximum DS0s is dependent on WAN data rate (T1
max is 24, E1 is 31). This is a tri-state output, high impedance when
RVDEN is high. This signal is only available on the DS33W41 and
DS33W11.
Receive Voice Clock Input. Receive clock that times RVDATA signal.
May be gapped. Maximum clock speed 52MHz. This signal is only
available on the DS33W41 and DS33W11.
FUNCTION
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