DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 59

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.14.1 Full Duplex Flow control
Automatic flow control is governed by the LAN Queue high watermark in AR.LQW, and is enabled per LAN Queue
in the SU.LQXPC register. This allows the user to enable or disable flow control for each of the four mapped
PCP/DSCP priorities. When the LAN queue threshold is exceeded on which flow control is enabled, the device will
send a pause frame with the timer value programmed in SU.MACFCR.PT[15:0] when in full duplex, or a jamming
signal in half duplex. More information on configuring the queues, see Section 8.9.3. Also see the SU.MACFCR
register definition for recommended flow control settings.
The pause frame causes the distant transmitter to “pause for a time” before starting transmission again. The device
will send a pause frame as the queue has crossed the threshold defined in AR.LQW. The pause control frame is
retransmitted every 16.4us, 164us, or 1.64ms, depending on the settings in SU.MACFCR.PLT. The receive queue
could keep growing if the round trip delay is greater than the Pause time. Pause control will only take care of
temporary congestion it does not take care of systems where the traffic throughput is too high for the queue sizes
selected. If the flow control is not effective the receive queue will eventually overflow. This is indicated in
SU.LIQOS. If the receive queue is overflowed any new frames will not be received until the overflow condition is
corrected..
The user has the option of not enabling automatic flow control. In this case the thresholds and corresponding
interrupt mechanism to send pause frame by writing to the FCB bit in the MAC flow control register SU.MACFCR.
This allows the user to set not only the watermarks but also to decide when to send a pause frame or not based on
watermark crossings.
On the receive side the user has control over whether to respond to the pause frame sent by the distant end
(SU.MACFCR.RFE bit). On the Transmit queue the user has the option of setting high and low thresholds and
corresponding interrupts. There is no automatic flow control mechanism for data received from the Serial
side waiting for transmission over the Ethernet interface during times of heavy Ethernet congestion.
8.14.2 Half Duplex Flow control
Half duplex flow control functions like Full Duplex flow control, but a jamming sequence is used to exert
backpressure on the transmitting node rather than Pause control frames. The receiving node jams the first 4 bytes
of a frame that are received from the MAC in order to cause a collision detection at the distant end. In both
100Mbps and 10Mbps MII/RMII modes, 4 bytes are jammed upon reception of a new frame. Note that the jamming
mechanism does not jam the frame that is being received during the watermark crossing, but will wait to jam the
next frame after the AR.LQW is crossed. If the queue remains above the threshold, received frames will continue
to be jammed. This jam sequence is stopped when the queue falls below the threshold in AR.LQW.
Rev: 063008
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