PSD311B-70J STMicroelectronics, PSD311B-70J Datasheet - Page 33

• Manufacturer Part Number: PSD311B-70J
• Description: IC MCU PROG 256KB 5V 70NS 44PLCC
• Manufacturer: STMicroelectronics

Specifications of PSD311B-70J

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 44-PLCC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3691

16.0
Power
Management
15.0
Security Mode
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PSD3XX Family
Security Mode in the PSD3XX locks the contents of PAD A, PAD B, and all the configuration
bits. The EPROM, optional SRAM, and I/O contents can be accessed only through the
PAD. The Security Mode must be set by PSDsoft prior to run-time. The Security Bit can only
be erased on the UV parts using a full-chip erase. If Security Mode is enabled, the contents
of the PSD3XX can not be uploaded (copied) on a device programmer.
PSDs from all PSD3XX families use Zero-power memory techniques that place memory
into Standby Mode between MCU accesses. The memory becomes active briefly after an
address transition, then delivers new data to the outputs, latches the outputs, and returns to
Standby. This is done automatically and the designer has to do nothing special to benefit
from this feature.
In addition to the benefits of Zero-power memory technology, there are ways to gain addi-
tional savings. The following factors determine how much current the entire PSD device
uses:
The total current consumption for the PSD is calculated by summing the currents from
memory, PAD logic, and I/O pins, based on your design parameters and the power
management options used.
16.1 CSI Input
Driving the CSI pin inactive (logic 1) disables the inputs of the PSD and forces the entire
PSD to enter Power-down Mode, independent of any transition on the MCU bus (address
and control) or other PSD inputs. During this time, the PSD device draws only standby
current (micro-amps). Alternately, driving a logic 0 on the CSI pin returns the PSD to normal
operation. See Tables 7A and 7B for information on signal states during Power-down Mode.
The CSI pin feature is available only if enabled in the PSDsoft Configuration utility.
16.2 CMiser bit
In addition to power savings resulting from the Zero-power technology used in the memory,
the CMiser feature saves even more power under certain conditions. Savings are significant
when the PSD is configured for an 8-bit data path because the CMiser feature turns off half
of the array when memory is being accessed (the memory is divided internally into odd and
even arrays). See the DC characteristics table for current usage related to the CMiser bit.
You should keep the following in mind when using this bit:
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Use of CSI (Chip Select Input)
Setting of the CMiser bit
Setting of the Turbo Bit (ZPSD only)
The number of product terms used in the PAD
The composite frequency of the input signals to the PAD
The loading on I/O pins.
Setting of this bit is accomplished with PSDsoft at the design stage, prior to run-time.
Memory access times are extended by 10 nsec for standard voltage (non-V) devices,
and 20 nsec for low voltage (V) devices.
EPROM access: although CMiser offers significant power savings in 8-bit mode
(~50%), CMiser contributes no additional power savings when the PSD is configured
for 16-bits.
SRAM access: CMiser reduces power consumption of PSDs configured for either 8-bit
or 16-bit operation.