PSD311B-70J STMicroelectronics, PSD311B-70J Datasheet - Page 67

• Manufacturer Part Number: PSD311B-70J
• Description: IC MCU PROG 256KB 5V 70NS 44PLCC
• Manufacturer: STMicroelectronics

Specifications of PSD311B-70J

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 44-PLCC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3691

Figure 40. Port A as AD0–AD7 Timing (Track Mode) Using R/W, E or R/W, DS (PSD3X2/3X3)
64
PSD3XX Family
Notes for
Timing
Diagrams
RD/E/DS as DS
RD/E/DS as E
RD/E/DS as E
RD/E/DS as E
RD/E/DS as E
R/W as R/W
Multiplexed
PAD Inputs
WR/V
PAD Input
PA0-PA7
A0/AD0-
A7/AD7
Direct
CSOi
or AS
PP
(1,4)
(5,7)
(3,6)
AS
or
2
1
23
2. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): A0/AD0–A15/AD15,
3. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C
4. CSADOUT1, which internally enables the address transfer to Port A, should be derived only from direct PAD
5. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively, can be
6. The write operation signals are included in the CSOi expression.
7. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in the multiplexed
8. CSOi product terms can include any of the PAD input signals shown in Figure 3, except for reset and CSI.
1. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or
STABLE INPUT
2
ADDRESS
R/W, transparent PC0–PC2, ALE in non-multiplexed modes.
CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2.
(CS8–CS10).
input signals, otherwise the address propagation delay is slowed down.
derived from any combination of direct PAD inputs and multiplexed PAD inputs.
modes: A11/AD11–A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2.
ADR OUT
24
3
STABLE INPUT
35
33
READ CYCLE
25
DATA IN
12
DATA VALID
26
32
34
1
23
2
STABLE INPUT
ADDRESS
ADR OUT
STABLE INPUT
24
WRITE CYCLE
3
35
33
28
27
12
WRITTEN
32
32
32
DATA
DATA
OUT
29
34