DP83266VF National Semiconductor, DP83266VF Datasheet - Page 100

• Manufacturer Part Number: DP83266VF
• Description: IC MEDIA ACSS CTRL INTF 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83266VF

• Applications: *
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 160-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83266VF

Bit
D0
D1
D2
D3
D4
D5
D6
D7
D2 –D1
D4 –D7
7 0 Control Information
No Space Notify Register (NSNR)
The No Space Notify Register (NSNR) is used to enable attentions in the No Space Attention Register (NSAR) If a bit in
Register NSNR is set to One the corresponding bit in Register NSAR will be applied to the Master Attention Register which can
be used to generate an interrupt to the host
All bits in this register are set to Zero upon reset
Access Rules
Register Bits
Limit Address Register (LAR)
The Limit Address Register (LAR) is used to program the parameters for an LMOP (Limit RAM Operation) service function
This register is not altered upon reset
Access Rules
Register Bits
Bit
D0
D3
NSR0N
LRA3
D7
D7
Address
Address
Symbol
NSI2N
LDI2N
NSI1N
LDI1N
NSI0N
LDI0N
NSR1N
NSR0N
10Bh
10Ch
LRD8
RES
LMRW
LRA3–LRA0
Symbol
NSR1N
LRA2
D6
D6
No Status Space on ICHN2 Notify This bit is used to enable the NSI2 bit in Register NSAR
Low Data Space on ICHN2 Notify This bit is used to enable the LDI2 bit in Register NSAR
No Status Space on ICHN2 Notify This bit is used to enable the NSI1 bit in Register NSAR
Low Data Space on ICHN2 Notify This bit is used to enable the LDI1 bit in Register NSAR
No Status Space on ICHN2 Notify This bit is used to enable the NSI0 bit in Register NSAR
Low Data Space on ICHN2 Notify This bit is used to enable the LDI0 bit in Register NSAR
No Status Space on ICHN2 Notify This bit is used to enable the NSR1 bit in Register NSAR
Low Data Space on ICHN2 Notify This bit is used to enable the NSR0 bit in Register NSAR
Always
Always
Read
Read
LDI0N
LRA1
Limit RAM Data Bit 8 This bit contains the most-significant data bit read or written from the
addressed limit RAM Register Bits LDR8 and LDR7 are ‘‘don’t cares’’ when using small (1 kByte)
queues
Reserved
LMOP Read Write This bit determines whether a LMOP service function will be a read
(LMRW)
Limit RAM Register Address Used to program the Limit RAM Register address for a subsequent
LMOP service function
D5
D5
e
NSI0N
1) or write (LMRW
LRA0
(Continued)
D4
D4
Always
Always
Write
Write
LMRW
LDI1N
D3
D3
e
0)
100
NSI1N
RES
D2
D2
Description
Description
LDI2N
RES
D1
D1
NSI2N
LRD8
D0
D0