DP83266VF National Semiconductor, DP83266VF Datasheet - Page 49

• Manufacturer Part Number: DP83266VF
• Description: IC MEDIA ACSS CTRL INTF 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83266VF

• Applications: *
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 160-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83266VF

7 0 Control Information
09C–09E
080 –086
088 –092
094 –096
Addr
0AA
0AB
0AC
0AD
0AE
0AF
087
093
097
098
099
09A
09B
09F
0A0
0A1
0A2
0A3
0A4
0A5
0A6
0A7
0A8
0A9
Reserved
THSH1
Reserved
TMAX
Reserved
TVX
TNEG0
TNEG1
TNEG2
TNEG3
Reserved
LTCT
FRCT0
FRCT1
FRCT2
FRCT3
EICT0
EICT1
EICT2
EICT3
LFCT0
LFCT1
LFCT2
LFCT3
FCCT0
FCCT1
FCCT2
FCCT3
Name
Null(7–4) THSH1(3 – 0)
Null(7–4) TMAX(3 – 0)
Null(7–4) TVX(3–0)
TNEG(31–24)
TNEG(23–16)
TNEG(15–8)
TNEG(7–0)
LTCT(7–0)
Zero(31–24)
Null(7–4) FRCT(19– 16)
FRCT(15–8)
FRCT(7–0)
Zero(31–24)
Null(7–4) EICT(19 – 16)
EICT(15–8)
EICT(7–0)
Zero(31–24)
Null(7–4) LFCT(19 – 16)
LFCT(15–8)
LFCT(7–0)
Zero(31–24)
Null(7–4) FCCT(19– 16)
FCCT(15–8)
FCCT(7–0)
Register Contents
TABLE 7-7 MAC Counters and Timer Thresholds
(Continued)
49
Note 1 Null(7–4) indicates that these bits are forced to zero on reads and
are ignored on writes
Note 2 The value obtained on reads from reserved locations is not speci-
fied
Note 3 On Master Reset the event counters are not cleared
The event counters are 20-bit counters and are read
through three control accesses In order to guarantee a
consistent snapshot whenever byte 3 of an event counter is
read byte 1 and byte 2 of the counters are loaded into a
holding register Byte 1 and byte 2 may then be read from
the holding register A single holding register is shared by all
of the counters but (for convenience) is accessible at sever-
al places within the address space Consistent readings
across counters can be accomplished using the Counter
Increment Latch Register (CILR)
The event counters are not reset as a result of a Master
Reset This may be done by either reading the counters out
and keeping track relative to the initial value read or by
writing a value to all of the counters in stop mode The
counters may be written in any order With some excep-
tions interrupts are available when the counters increment
or wraparound
Addr
0BC
0BD
0B0
0B1
0B2
0B3
0B4
0B5
0B6
0B7
0B8
0B9
0BA
0BB
0BE
0BF
FNCT0
FNCT1
FNCT2
FNCT3
FTCT0
FTCT1
FTCT2
FTCT3
TKCT0
TKCT1
TKCT2
TKCT3
RLCT0
RLCT1
RLCT2
RLCT3
Name
Zero(31– 24)
Null(7– 4) FNCT(19– 16)
FNCT(15– 8)
FNCT(7– 0)
Zero(31– 24)
Null(7– 4) FTCT(19– 16)
FTCT(15– 8)
FTCT(7– 0)
Zero(31– 24)
Null(7– 4) TKCT(19– 16)
TKCT(15– 8)
TKCT(7– 0)
Zero(31 – 24)
Null(7– 4) RLCT(19 – 16)
RLCT(15– 8)
RLCT(7– 0)
Register Contents