DP83266VF National Semiconductor, DP83266VF Datasheet - Page 8

• Manufacturer Part Number: DP83266VF
• Description: IC MEDIA ACSS CTRL INTF 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83266VF

• Applications: *
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 160-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83266VF

3 0 Architectural Description
During frame transmission the Transmitter performs the fol-
lowing functions
During frame repeating the Transmitter performs the follow-
ing functions
Whether transmitting or repeating frames the Transmitter
also performs the following functions
Data is presented from the Transmitter to the PLAYER
device in byte stream format (PH Request)
3 2 3 MAC Parameter RAM
The MAC Parameter RAM is a dual port RAM that contains
MAC parameters such as the station’s short and long ad-
dresses These parameters are initialized via the Control
Interface Both the Receiver and Transmitter Blocks access
the RAM
The Receiver uses these parameters to compare addresses
in incoming frames with the individual and group addresses
stored in the Parameter RAM
The Transmitter uses the Parameter RAM for generating the
Source Address for all frames (except when Source Ad-
dress Transparency is enabled) and for the Destination Ad-
dress and Information fields on Claim and Beacon frames
3 2 4 Counters Timers
The Counter Timer Block maintains all of the counters and
timers required by the ANSI X3T9 5 MAC standard
Events which occur too rapidly for software to count such
as the various Frame Counts are included in the Event
Counters The size of the wrap around counters has been
chosen to require minimal software intervention even under
marginal operating conditions Most of the counters incre-
ment in response to events detected by the Receiver The
counters are readable via the Control Interface
The Token Rotation and Token Holding Timers which are
used to implement the Timed Token Protocol are contained
within the Timer Block
3 3 DATA STRUCTURES
3 3 1 Data Types
The architecture of the MACSI device defines two basic
types of objects Data Units and Descriptors A Data Unit is
a group of contiguous bytes which forms all or part of a
frame A Descriptor is a two-word (64-bit) control object that
provides addressing information and control status informa-
tion about MACSI device operations
Captures a token to gain the right to transmit
Transmits one or more frames
Generates the Frame Check Sequence and appends it at
the end of the frame
Generates the Frame Status field that is transmitted at
the end of the frame
Issues the token at the end of frame transmission
Repeats the received frame and modifies the Frame
Status field at the end of the frame as specified by the
standard
Strips the frame(s) that are transmitted by this station
Generates Idle symbols between frames
(Continued)
a
8
Data and Descriptor objects may consist of one or more
parts where each part is contiguous and wholly contained
within a memory page Descriptor pages are selectable as
all 1 kBytes or all 4 kBytes Data Units are described by
Descriptors with a pointer and a count A single Data Unit
may not cross a 4k boundary All Descriptors may be
marked as First Middle Last or Only Thus multiple De-
scriptors may be combined to describe a single entity (i e
one frame) A single-part object consists of one Only Part a
multiple-part object consists of one First Part zero or more
Middle Parts and one Last Part In Descriptor names the
object part is denoted in a suffix preceded by a dot Thus
an Input Data Unit Descriptor (IDUD) which describes the
last Data Unit of a frame received from the ring is called an
IDUD Last
A Data Unit is stored in contiguous locations within a single
4 kByte page in memory Multiple-part Data Units are stored
in separate and not necessarily contiguous 4 kByte pages
Descriptors are stored in contiguous locations in Queues
and Lists where each Queue occupies a single 1 kByte or
4 kByte memory page aligned on the queue-size boundary
For Queues an access to the next location after the end of
a page will automatically wrap-around and access the first
location in the page
Data Units are transferred between the MACSI’s Service
Engine and Ring Engine via five simplex Channels three
used for Indicate (receive) data and two for Request (trans-
mit) data Parts of frames received from the ring and copied
to memory are called Input Data Units (IDUs) parts of
frames read from memory to be transmitted to the ring are
called Output Data Units (ODUs)
Descriptors are transferred between the MACSI device and
Host via the ABus whose operation is for the most part
transparent to the user There are five Descriptor types rec-
ognized by the MACSI device Input Data Unit Descriptors
(IDUDs) Output Data Unit Descriptors (ODUDs) Pool
Space Descriptors (PSPs) Request Descriptors (REQs)
and Confirmation Message Descriptors (CNFs)
Input and Output Data Unit Descriptors describe a single
Data Unit part i e its address (page number and offset) its
size in bytes and its part (Only First Middle or Last)
Frames consisting of a single part are described by a Des-
criptor Only frames consisting of multiple parts are de-
scribed by a single Descriptor First zero or more Descrip-
tor Middles and a single Descriptor Last
Every Output Data Unit part is described by an ODUD Out-
put Data Unit Descriptors are fetched from memory so that
frame parts can be assembled for transmission
Every Input Data Unit part is described by an Input Data Unit
Descriptor (IDUD) Input Data Unit Descriptors are generat-
ed on Indicate Channels to describe where the MACSI de-
vice wrote each frame part and to report status for the
frame
Request Descriptors (REQs) are written by the user to spec-
ify the operational parameters for the MACSI device Re-
quest operations Request Descriptors also contain the start
address of part of a stream of ODUDs and the number of
frames represented by the ODUD stream part (i e the num-
ber of ODUD Last descriptors) Typically the user will define
a single Request Object consisting of multiple frames of the
same request and service class frame control and expect-
ed status