TP3420AN308 National Semiconductor, TP3420AN308 Datasheet - Page 28

• Manufacturer Part Number: TP3420AN308
• Description: IC INTERFACE DEVICE ISDN 20-DIP
• Manufacturer: National Semiconductor

Specifications of TP3420AN308

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 20-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *TP3420AN308

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Definitions and Timing
Conventions
V
Threshold Region The threshold region is the range of in-
Valid Signal
Invalid Signal
TIMING CONVENTIONS
For the purposes of this timing specification the following
conventions apply:
Input Signals
Period
Rise Time
Fall Time
Pulse Width High The high pulse width is designated as
Appendix A
FIRMWARE GUIDELINES FOR HANDLING SC1/Q AND
SC2 MAINTENANCE MESSAGES
This application note describes software guidelines that
make use of TP3420A hardware features designed to sup-
port the handling of the newly defined maintenance channels
SC1/Q and SC2. Please refer to the TP3420A datasheet and
the T1.605-1991 specification for explanations of the SC1/Q
and SC2 messages.
SC1 TRANSMITTER CONTROL IN NT UNIT
The microcontroller software must keep a list of flags for SC1
messages of lower priority that need to be sent for 6 frames,
in the following priority order as they occur: ST reports, LB
indications, LRS, DOI, IDLE. These messages should be
sent through the MFT1L register. The software should also
keep a list of flags for the high priority messages that have to
be sent once in the following priority order: LP, FECV, and
DTSE commands. These messages should be sent through
the MFT1H register. As part of the TP3420A initialization, the
software should write the MFC6E command to cause the de-
vice to generate the MFC interrupt every 30 ms, and this in-
terrupt status should be used to synchronize the SC1L and
any SC2 messages.
OL
All input signals may be characterized
as: V
t
The period of clock signal is designated
as t
monic of the clock signal being specified.
Rise times are designated as t
yy represents a mnemonic of the signal
whose rise time is being specified. t
measured from V
Fall times are designated as t
yy represents a mnemonic of the signal
whose fall time is being specified. t
measured from V
V
which an output placed in a logical zero
state will converge when loaded at the
maximum specified load current.
put voltages between V
A signal is Valid if it is in one of the valid
logic states, (i.e. above V
V
deemed valid at the instant it enters a
valid state.
A signal is Invalid if it is not in a valid
logic state, i.e. when it is in the threshold
region between V
specifications, a signal is deemed invalid
at the instant it enters the threshold re-
gion.
F
OL
IL
<
(Continued)
). In timing specifications, a signal is
Pxx
is the maximum d.c. output level to
10 ns.
L
where xx represents the mne-
= 0.4V, V
H
IL
IH
IL
to V
= 2.4V, t
to V
and V
IH
IL
IL
.
.
and V
IH
IH
R
. In timing
Ryy
Fyy
or below
<
IH
, where
, where
10 ns,
.
Ryy
Fyy
is
is
28
Pulse Width Low
Setup Time
Hold Time
Delay Time
Events and conditions that cause SC1 messages to be gen-
erated arise from 3 different sources, the S interface loop,
the U interface loop or from within the NT unit itself. S Loop
conditions can cause the RMFE indication to indicate a code
violation that must be reported to the TE by the FECV mes-
sage. U loop conditions are communicated to the TE by the
LRS, DOI and the DTSE messages. The NT local microcon-
troller will generate the messages for the ST reports, LB in-
dications, LP and the IDLE.
Each 30 ms tick, the software should service the list of flags
and go down the priority chain. The command (for MFT1L
register) corresponding to the highest flag is sent to the
MFT1L register and the flag is reset. The MFT1L commands
may be updated at every 30 ms tick if any of the relevant
flags are set. If a DTSE interrupt is received from the U inter-
face, this command is immediately loaded into the MFT1H
register. Similarly, a local RMFE interrupt should be re-
sponded with a FECV command through the MFT1H register
immediately. A double buffer has been implemented in the
MFT1H register to ensure that 2 commands can be queued
and each will be sent for 1 multiframe. The device has 2 4-bit
register FIFOs. At every multiframe boundary, MFT1H FIFO
t
monic of the input or output signal whose
pulse width is being specified. High
pulse widths are measured from V
V
The low pulse width is designated as
t
monic of the input or output signal whose
pulse width is being specified. Low pulse
widths are measured from V
Setup times are designated as t
where ww represents the mnemonic of
the input signal whose setup time is be-
ing specified relative to a clock or strobe
input represented by mnemonic xx.
Setup times are measured from the ww
Valid to xx Invalid.
Hold times are designated as t
where ww represents the mnemonic of
the input signal whose hold time is being
specified relative to a clock or strobe in-
put represented by mnemonic xx. Hold
times are measured from xx Valid to ww
Invalid.
Delay
t
mnemonic of the input reference signal
and yy represents the mnemonic of the
output signal whose timing is being
specified relative to xx. The mnemonic
may optionally be terminated by an H or
L to specify the high going or low going
transition of the output signal. Maximum
delay times are measured from xx Valid
to yy Valid. Minimum delay times are
measured from xx Valid to yy Invalid.
This parameter is tested under the load
conditions specified in the Conditions
column of the Timing Specifications sec-
tion of this data sheet.
WzzH
WzzL
Dxxyy
IH
.
, where zz represents the mne-
, where zz represents the mne-
[ |H|L], where xx represents the
times
are
designated
IL
to V
Hxxww
Swwxx
IL
IH
.
as
to
,
,