HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 101

• Manufacturer Part Number: HD64570F16
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F16

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit 7 (IPC: Interrupt Priority Control): Controls the priority order of interrupt sources. This bit
is cleared to 0 at a reset.
IPC = 0: MSCI interrupt sources have higher priority than DMAC interrupt sources.
IPC = 1: DMAC interrupt sources have higher priority than MSCI interrupt sources.
Bit 6, Bit 5 (IAK1, IAK0: Interrupt Acknowledge Cycle): Select the type of acknowledge
cycle. These bits are cleared to 0 at a reset.
IAK1, IAK0 = 0, 0:
IAK1, IAK0 = 0, 1:
bus lines D
undefined.
IAK1, IAK0 =1, 0:
IAK1, IAK0 =1, 1:
Bit 4 (VOS: Vector Output Select): Selects which vector to output in a single or double
acknowledge cycle. This bit is cleared to 0 at a reset.
VOS = 0: The interrupt vector register is selected. The unmodified IVR contents are output in a
VOS = 1: The interrupt modified vector register is selected. The IMVR contents are output in a
Bits 3 0: Reserved. These bits always read 0 and must be set to 0.
7
single or double acknowledge cycle.
single or double acknowledge cycle.
to D
0
at the first active (low) input on the INTA line. Output for D
Non-acknowledge cycle; the data bus is left in the high-impedance state
even when the INTA line is driven active low. Although the INTA line
input is ignored if this type of acknowledge cycle is selected, this line
should be pulled up to V
Double acknowledge cycle; the data bus is left in the high-impedance state
at the first active (low) input on the INTA line. The value in IVR or IMVR
is output on data bus lines D
INTA line. Output for D
Reserved.
Single acknowledge cycle; the value in IVR or IMVR is output on data
CC
15
.
to D
7
to D
8
is undefined.
0
at the second active (low) input on the
Rev. 0, 07/98, page 85 of 453
15
to D
8
is