HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 316
HD64570F16
Manufacturer Part Number
HD64570F16
Description
IC SCA SRL COMM ADAPTER 88QFP
Manufacturer
Renesas Electronics America
Datasheet
1.HD64570F16.pdf
(469 pages)
Specifications of HD64570F16
Applications
ISDN
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
88-QFP
Mounting Type
Surface Mount
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
HD64570F16
Manufacturer:
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Quantity:
10 000
Part Number:
HD64570F16
Manufacturer:
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Quantity:
20 000
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Part Number:
HD64570F16V
Manufacturer:
INFINEON
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Table 6.11 DMAC Characteristics in CPU Mode 1*
Mode
Single-block
transfer mode
Chained-block
transfer mode
Notes: 1 memory cycle = 3 states
6.5
The DMAC can issue DMIA (error) and DMIB (normal end) interrupt requests to the MPU.
These requests are indicated by the DMA status register (DSR) and are enabled or disabled by the
DMA interrupt enable register (DIR). Table 6.12 lists interrupt types, interrupt sources, and
clearing their procedures.
Rev. 0, 07/98, page 300 of 453
Internal states are used for SCA internal operations.
1. Units are states unless otherwise specified. The values shown here are valid when no
2. Before entering a data transfer cycle, the DMAC requires some set-up time to read the
3. 20 states = 5 memory cycles (15 states) + 5 internal states
4. 21 states = 5 memory cycles (15 states) + 6 internal states (in the middle of a frame)
5. 18 states = 3 memory cycles (9 states) + 9 internal states
6. 26 states = 5 memory cycles (15 states) + 11 internal states
7. 32 states = 8 memory cycles (24 states) + 8 internal states
8. 33 states = 8 memory cycles (24 states) + 9 internal states (in the middle of a frame)
9. 23 states = 5 memory cycles (15 states) + 8 internal states
10. 34 states = 8 memory cycles (24 states) + 10 internal states
Interrupts
wait state is inserted.
first descriptor.
25 states = 5 memory cycles (15 states) + 10 internal states (at the end of a frame)
37 states = 8 memory cycles (24 states) + 13 internal states (at the end of a frame)
Transfer Direction
Memory to MSCI
MSCI to memory
Memory to MSCI
(transmission)
MSCI to memory
(reception)
DMA Transfer Rate
(states/byte)
3
3
3
3
1
DMA Transfer
Set-Up Time*
—
—
32*
23*
7
9
2
DMAC Buffer
Switching Time
—
—
33/37*
34*
10
8
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