PEB2045N-VA3TR Infineon Technologies, PEB2045N-VA3TR Datasheet - Page 17

• Manufacturer Part Number: PEB2045N-VA3TR
• Description: IC SWITCH MEM TIME CMOS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PEB2045N-VA3TR

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 44-PLCC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEB2045N-VA3INTR; PEB2045N-VA3TR

Output Buffer
The output buffer rearranges the data read from the speech memory. It basically converts the
parallel data to serial data. Depending on the tristate control signal from the timing control block the
output buffer outputs the data or switches the line to high impedance.
The mode register (MOD) bits MI1, MI0, MO1 and MO0 control this process. The possible output
modes are listed in table 2.
Table 2
Possible Output Modes
Output Modes
8
4
2
1
2
Figure 11 shows, when the single bits are output. In standard configuration they are clocked off at
the rising clock edge at the beginning of the considered bit period. Time-slot 0 starts two
the falling edge of the SP pulse.
In primary access configuration the even output lines are affected by the XS2, XS1, XS0 and XFE
entries in the clock shift register. The output frame is synchronized with the rising edge of the SP-
signal.
Assuming a CSR entry X0
Programming the XS2, XS1 and XS0 bits with a value deviating from binary 000 the output frame
is delayed by 8
frame by 7-bit periods relative to the rising SP-pulse edge.
Programming CSR:(XXXXXXX1) the output frame is delayed by another half a device clock period.
In figure 11 the outputting instants are shown for a device clock of 4096 and 8192 kHz and a
CSR:(XXXX0001).
The last line in figure 11 shows an even 8192-kbit/s output line for the CSR entry (XXXX0111) and
a 8192-kHz device clock. The output frame is delayed by 5 1/2-bit periods. For further examples
refer to figure 21.
If the CSR is programmed such that XS2 is identical to RS2, XS1 to RS1, XS0 to RS0 and RRE to
XFE the time-slot boundaries of input and output coincide. Programming XS2, XS1, XS0 as well as
RS2, RS1, RS0 to logical 0 input and output time-slots coincide. Otherwise the system interface
output frame starts one time-slot after the system interface input. This can be seen comparing for
example the lines 0100XXXX and XXXX0100 in figure 21.
Semiconductor Group
8192
4096
+
+
D
- (XS2, XS1, XS0)
2048
4096
8192
4
4
2048
2048
H
the output frame starts with the rising edge of the SP pulse.
kbit/s
kbit/s
kbit/s
kbit/s
kbit/s
B
bit periods. E.g., a CSR entry of (XXXX0010) delays the output
17
Type
Single mode
Single mode
Single mode
Mixed mode
Mixed mode
PEB 2045
PEF 2045
t
CP8
before