PEB2045N-VA3TR Infineon Technologies, PEB2045N-VA3TR Datasheet - Page 26

• Manufacturer Part Number: PEB2045N-VA3TR
• Description: IC SWITCH MEM TIME CMOS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PEB2045N-VA3TR

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 44-PLCC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PEB2045N-VA3INTR; PEB2045N-VA3TR

Figure 14
SYP Duration for N = 2
The device is synchronized after 3 SP pulses (see chapter 3.2).
2.4
A logical 0 in the CFS bit of the configuration register selects the PEx 2045 for primary access
applications. In this case the PEx 2045 is an interface device connecting a standard PCM interface
(system interface) with another PCM interface e.g. an intermediate interface for connections to
primary loops (synchronous interface). For both a serial interface is provided.
The frame for all input- and output lines starts with the rising edge of the SP signal.
In the primary access mode the signals TSC0, TSC1, TSC2 and TSC3 indicate when the
associated system interface output is valid. The signal DCL supplies a 2-MHz clock which can be
used for other devices at the synchronous interface, e.g. the High Level Serial Communication
Controller HSCC (SAB 82520).
In the primary access configuration only those modes which support at least 4 input and 4 output
lines at 2048 kbit/s can be used. These are the modes MI1, MI0, MO1, MO0 = 0
table 9). Programming the CM in the primary access configuration is described in tables 17 and 18.
The least significant 2 bits of the data byte and the least significant bit of the address byte determine
the type of interface, the more significant bits define the logical line number and time-slot number.
The following example explains how to program the CM in primary access configuration and how
the clock shift works:
Semiconductor Group
The synchronous 2048-kbit/s interface consists of four input and four output lines with a bit rate
of 2048-kbit/s. This interface can be used to connect the PEx 2045 to up to four primary trunk
lines via coding / decoding devices with frame alignment function (e.g. PEB 2035 ACFA) and line
transceivers with clock and data recovery (e.g. PEB 2235 IPAT) and to signaling processors (e.g.
the SAB 82520 HSCC).
The system interface is not confined to one data rate but can operate at the full choice of the
PEx 2045 data rates: 2048, 4096 and 8192 kbit/s. A clock shift in a range of 7 1/2 clock steps with
half clock step resolution may be programmed independently for inputs and outputs.
Primary Access Configuration
26
H
, A
PEB 2045
PEF 2045
H
, F
H
(see