HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 12
HSDC-JAKIT1W2/DB
Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r
Datasheets
1.ADC1413D125HNC15.pdf
(43 pages)
2.DAC1408D650HNC15.pdf
(98 pages)
3.HSDC-JAKIT1W2DB.pdf
(2 pages)
4.HSDC-JAKIT1W2DB.pdf
(2 pages)
5.HSDC-JAKIT1W2DB.pdf
(3 pages)
Specifications of HSDC-JAKIT1W2/DB
Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
NXP Semiconductors
ADC1413D_SER
Product data sheet
10.3 Serial output timing
The eye diagram of the serial output is shown in
are:
Fig 3.
Fig 4.
•
•
•
3.125 Gbps data rate
T
DC coupling with two different receiver common-mode voltages
amb
= 25 °C
Eye diagram at 1 V receiver common-mode
Eye diagram at 2 V receiver common-mode
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 February 2011
Dual 14-bit ADC; serial JESD204A interface
Figure 3
ADC1413D series
and
Figure
4. Test conditions
© NXP B.V. 2011. All rights reserved.
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