HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 20
HSDC-JAKIT1W2/DB
Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r
Datasheets
1.ADC1413D125HNC15.pdf
(43 pages)
2.DAC1408D650HNC15.pdf
(98 pages)
3.HSDC-JAKIT1W2DB.pdf
(2 pages)
4.HSDC-JAKIT1W2DB.pdf
(2 pages)
5.HSDC-JAKIT1W2DB.pdf
(3 pages)
Specifications of HSDC-JAKIT1W2/DB
Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
NXP Semiconductors
ADC1413D_SER
Product data sheet
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in
voltage of the differential input stage is set via 5 k internal resistors.
Fig 17. Differential clock input
Fig 18. Equivalent input circuit
a. Sine clock input
c. LVPECL clock input
V
CLKM
CLKP
cm(clk)
clock input
Sine
= common-mode voltage of the differential input stage.
All information provided in this document is subject to legal disclaimers.
package
Rev. 5 — 9 February 2011
005aaa173
CLKM
CLKP
ESD
clock input
LVPECL
parasitics
Dual 14-bit ADC; serial JESD204A interface
005aaa172
CLKM
CLKP
clock input
b. Sine clock input (with transformer)
ADC1413D series
Sine
SE_SEL
Figure
5 kΩ
V
cm(clk)
18. The common-mode
SE_SEL
5 kΩ
© NXP B.V. 2011. All rights reserved.
005aaa081
005aaa054
CLKM
CLKP
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