EA-XPR-007 Embedded Artists, EA-XPR-007 Datasheet - Page 48

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EA-XPR-007

Manufacturer Part Number
EA-XPR-007
Description
BOARD LPCXPRESSO LPC11U14
Manufacturer
Embedded Artists
Datasheets

Specifications of EA-XPR-007

Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
Table 16.
[1]
[2]
[3]
[4]
LPC11U1X
Objective data sheet
Symbol
SSP master
T
t
t
t
t
SSP slave
T
t
t
t
t
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
cy(clk)
cy(PCLK)
T
main clock frequency f
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
T
T
T
cy(clk)
amb
cy(clk)
amb
= 40 C to 85 C.
= 25 C; V
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
= 12  T
Dynamic characteristics: SSP pins in SPI mode
Parameter
clock cycle time
data set-up time
data hold time
data output valid time
data output hold time
PCLK cycle time
data set-up time
data hold time
data output valid time
data output hold time
10.6 SSP interface
cy(PCLK)
DD
= 3.3 V.
main
.
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
when only receiving
in SPI mode;
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
Conditions
when only transmitting
2.4 V  V
2.0 V  V
All information provided in this document is subject to legal disclaimers.
main
DD
DD
Rev. 1 — 11 April 2011
. The clock cycle time derived from the SPI bit rate T
 3.6 V
< 2.4 V
[1]
[1]
[2]
[2]
[2]
[2]
[2]
[3][4]
[3][4]
[3][4]
[3][4]
Min
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
-
<tbd>
<tbd>
<tbd>
<tbd>  T
<tbd>
-
-
32-bit ARM Cortex-M0 microcontroller
cy(PCLK)
+
Max
-
-
-
-
-
<tbd>
-
-
-
-
<tbd>  T
<tbd>
<tbd>  T
<tbd>
LPC11U1x
cy(clk)
cy(PCLK)
cy(PCLK)
© NXP B.V. 2011. All rights reserved.
is a function of the
+
+
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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