EVAL-ADF7023-JDB1Z Analog Devices Inc, EVAL-ADF7023-JDB1Z Datasheet - Page 58

• Manufacturer Part Number: EVAL-ADF7023-JDB1Z
• Description: BOARD EVAL ADF7023-JDB1Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB1Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

ADF7023-J
Smart Wake Mode
In this low power mode, the WUC, firmware timer, and smart
wake mode are employed to periodically listen for packets. To
enable this mode, the WUC and firmware timer should be
configured and smart wake mode (SWM) enabled (the SWM_EN
bit, Address 0x11A) before entering the PHY_SLEEP state. The
WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to
ensure that the BBRAM is retained. RSSI prequalification can
be optionally enabled (SWM_RSSI_QUAL = 1, Address 0x11A).
When RSSI prequalification is enabled, the ADF7023-J begins
searching for the preamble only if the RSSI measurement is
greater than the user-defined threshold.
The ADF7023-J is in the PHY_RX state for a duration deter-
mined by the RX_DWELL_TIME setting (Address 0x106).
If the ADF7023-J detects the preamble during the receive dwell
time, it searches for the sync word. If the sync word routine is
detected, the ADF7023-J loads the received data to packet RAM
and checks for a CRC and address match, if enabled. If any of
the receive packet interrupts has been set, the ADF7023-J
returns to the PHY_ON state and waits for a host command.
If the ADF7023-J receives preamble detection during the receive
dwell time but the remainder of the received packet extends
beyond the dwell time, the ADF7023-J extends the dwell time
until all of the packet is received or the packet is recognized as
invalid (for example, there is an incorrect sync word).
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This low power mode terminates when a valid packet interrupt
is received. Alternatively, this low power mode can be terminated
via a firmware timer timeout. This can be useful if certain radio
tasks (for example, IR calibration) or processor tasks must be
run periodically while in the low power mode.
The operation of this low power mode is illustrated in Figure 73.
Exiting Low Power Mode
As described in Figure 69, the ADF7023-J waits for a host
command on any of the termination conditions of the low power
mode. It is also possible to perform an asynchronous exit from
low power mode using the following procedure:
1.
2.
The host processor should then follow the initialization
procedure after a CMD_HW_RESET command, as described in
the Initialization section.
Bring the CS pin of the SPI low and wait until the MISO
output goes high.
Issue a CMD_HW_RESET command.