EVAL-ADF7023-JDB1Z Analog Devices Inc, EVAL-ADF7023-JDB1Z Datasheet - Page 71

• Manufacturer Part Number: EVAL-ADF7023-JDB1Z
• Description: BOARD EVAL ADF7023-JDB1Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB1Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

CLOCK RECOVERY
An oversampled digital clock and data recovery (CDR) PLL is
used to resynchronize the received bit stream to a local clock in
all modulation modes. The maximum symbol rate tolerance of
the CDR PLL is determined by the number of bit transitions in
the transmitted bit stream. For example, during reception of a
010101 preamble, the CDR achieves a maximum data rate
tolerance of ±3.0%. However, this tolerance is reduced during
recovery of the remainder of the packet where symbol transitions
may not be guaranteed to occur at regular intervals during the
payload data. To maximize data rate tolerance of the receiver’s
CDR, 8b/10b encoding or Manchester encoding should be
enabled, which guarantees a maximum number of contiguous
bits in the transmitted bit stream. Data whitening can also be
enabled on the ADF7023-J to break up long sequences of
contiguous data bit patterns.
Using 2FSK/GFSK/MSK/GMSK modulation, it is also possible
to tolerate uncoded payload data fields and payload data fields
with long run length coding constraints if the data rate tolerance
and packet length are both constrained. More details of CDR
operation using uncoded packet formats are discussed in the
AN-915
The CDR PLL of the ADF7023-J is optimized for fast acquisition of
the recovered symbols during preamble and typically achieves
bit synchronization within five symbol transitions of preamble.
RECOMMENDED RECEIVER SETTINGS FOR
2FSK/GFSK/MSK/GMSK
To optimize the ADF7023-J receiver performance and to ensure
the lowest possible packet error rate, it is recommended to use
the following configurations:
•
•
•
•
The recommended settings for AGC, AFC, preamble length,
and sync word are summarized in Table 41.
Recommended AGC Settings
To optimize the receiver for robust packet error rate performance,
when using minimum preamble length over the full input power
range, it is recommended to overwrite the default AGC settings
in the MCR memory. The recommended settings are as follows:
•
•
•
Set the recommended AGC low and high thresholds and
the AGC clock divide.
Set the recommended AFC Ki and Kp parameters.
Use a preamble length ≥ the minimum recommended
preamble length.
When the AGC is configured to lock on the sync word at
data rates greater than 200 kbps, it is recommended to set
the sync word error tolerance to one bit.
AGC_HIGH_THRESHOLD (Address 0x35F) = 0x78
AGC_LOW_THRESHOLD (Address 0x35E) = 0x46
AGC_CLK_DIVIDE (Address 0x32F) = 0x0F or 0x19
(depends on the data rate; see Table 41)
Application Note.
Rev. 0 | Page 71 of 100
MCR memory is not retained in PHY_SLEEP; therefore, to
allow the use of these optimized AGC settings in low power
mode applications, a static register fix can be used. An example
static register fix to write to the AGC settings in MCR memory
is shown in Table 40.
Note that the accuracy of the RSSI readback is degraded with
these modified settings.
Table 40. Example Static Register Fix for AGC Settings
BBRAM Register
0x128
(STATIC_REG_FIX)
0x12B
0x12C
0x12D
0x12E
0x12F
0x130
0x131
Recommended AFC Settings
The bandwidth of the AFC loop is controlled by the AFC_KI and
AFC_KP bits in the RADIO_CFG_11 register (Address 0x117).
To ensure optimum AFC accuracy while minimizing the AFC
settling time (and thus the required preamble length), the
AFC_KI and AFC_KP bits should be set as outlined in Table 41.
Recommended Preamble Length
When AFC is locked on preamble detection, the minimum
preamble length is between 40 bits and 60 bits depending on
the data rate. When AFC is set to lock on sync word detection,
the minimum preamble length is between 14 bits and 32 bits,
depending on the data rate. When AFC and preamble detection
are disabled, the minimum preamble length is dependent on the
AGC settling time and the CDR acquisition time and is between
8 bits and 24 bits, depending on the data rate. The required
preamble length for various data rates and receiver configurations
is summarized in Table 41.
Recommended Sync Word Tolerance
At data rates greater than 200 kbps and when the AGC is configured
to lock on the sync word, it is recommended to set the sync word
error tolerance to one bit (SYNC_ERROR_TOL = 1). This prevents
an AGC gain change during sync word reception causing a packet
loss by allowing one bit error in the received sync word.
Data
0x2B
0x5E
0x46
0x5F
0x78
0x2F
0x0F
0x00
Description
Pointer to BBRAM Address 0x12B
MCR Address 0x35E
Data to write to MCR Address
0x35E (sets AGC low threshold)
MCR Address 0x35F
Data to write to MCR Address
0x35F (sets AGC high threshold)
MCR Address 0x32F
Data to write to MCR Address
0x32F (sets AGC clock divide)
Ends static MCR register fixes
ADF7023-J