EVAL-ADF7023-JDB1Z Analog Devices Inc, EVAL-ADF7023-JDB1Z Datasheet - Page 72

• Manufacturer Part Number: EVAL-ADF7023-JDB1Z
• Description: BOARD EVAL ADF7023-JDB1Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB1Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

ADF7023-J
Table 41. Summary of Recommended AGC, AFC, Preamble Length, and Sync Word Error Tolerance for 2FSK/GFSK/MSK/GMSK
Data
Rate
(kbps)
300
200
150
100
50
38.4
9.6
1
1
2
3
4
5
Setup 1: AFC and AGC are configured to lock on preamble detection by setting AFC_LOCK_MODE = 3 and AGC_LOCK_MODE = 3.
Setup 2: AFC and AGC are configured to lock on sync word detection by setting AFC_LOCK_MODE = 3, AGC_LOCK_MODE = 3, and PREAMBLE_MATCH = 0.
Setup 3: AFC is disabled and AGC is configured to lock on sync word detection by setting AFC_LOCK_MODE = 1, AGC_LOCK_MODE = 3, and PREAMBLE_MATCH = 0.
For Setup 2 and Setup 3, sync word length is 24 bits. Sync word detect length has an impact on minimum preamble length.
The AGC high threshold is configured by writing to the AGC_HIGH_THRESHOLD register (Address 0x35F). The AGC low threshold is configured by writing to the
AGC_LOW_THRESHOLD register (Address 0x35E). The AGC clock divide is configured by writing to the AGC_CLK_DIVIDE register (Address 0x32F). Note that the
accuracy of the RSSI readback is degraded with these modified AGC threshold settings.
The AFC is enabled or disabled by writing to the AFC_LOCK_MODE setting in register RADIO_CFG_10 (Address 0x116). The AFC Ki and Kp parameters are configured
by writing to the AFC_KP and AFC_KI settings in the RADIO_CFG_11 register (Address 0x117).
The transmit preamble length (in bytes) is set by writing to the PREAMBLE_LEN register (Address 0x11D).
The sync word error tolerance (in bits) is set by writing to the SYNC_ERROR_TOL setting in the SYNC_CONTROL register (Address 0x120).
Frequency
Deviation
(kHz)
75
50
37.5
25
12.5
20
10
10
IF
BW
(kHz)
300
200
150
100
100
100
100
100
AFC
Pull-In
Range
(kHz)
±150
±100
±75
±50
±50
±50
±50
±50
Setup
1
2
3
1
1
1
1
1
2
3
1
1
1
1
1
High
Threshold
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
Rev. 0 | Page 72 of 100
Low
Threshold
0x46
0x46
0x46
0x46
0x46
0x46
0x46
0x46
0x46
0x46
0x46
0x46
0x46
0x46
AGC
2
Clock
Divide
0x0F
0x19
0x19
0x19
0x19
0x19
0x19
0x19
0x19
0x19
0x19
0x19
0x19
0x19
On/Off
On
On
Off
On
On
On
On
On
On
Off
Off
On
Off
On
AFC
Ki
7
8
7
7
7
7
7
7
7
7
3
Kp
3
3
3
3
3
3
3
3
3
3
Minimum
Preamble
Length
(Bits)
64
32
24
58
54
52
50
44
14
8
8
46
8
40
4
Sync
Word
Error
Tolerance
(Bits)
0
1
1
0
0
0
0
0
0
0
0
0
0
0
5