VRS51C1000-40-QG-ISPV2 Ramtron, VRS51C1000-40-QG-ISPV2 Datasheet - Page 11

• Manufacturer Part Number: VRS51C1000-40-QG-ISPV2
• Description: Microcontrollers (MCU) 64K+1K 40MHz 5V
• Manufacturer: Ramtron

Specifications of VRS51C1000-40-QG-ISPV2

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFP-44
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 128 B
• Height: 2 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 10 mm
• Lead Free Status / Rohs Status: Details

Windowed access to all the 1KB on-chip SRAM in the
range of 40h-7Fh is described in the following table.
T
Example: User writes #55h to address 203h:
______________________________________________________________________________________________
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ABLE
BS3
VRS51C1000
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
15: B
ANK MAPPING DIRECT ADDRESSING MODE
BS2
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
MOV
MOV
MOV
BS1
DBANK, #8CH
A, #55H
43H, A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BSO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00C0h-00FFh
01C0h-01FFh
02C0h-02FFh
0000h-003Fh
0040h-007Fh
0080h-00BFh
0100h-013Fh
0140h-017Fh
0200h-023Fh
0240h-027Fh
0280h-02BFh
0180h-01BFh
0C0h-0FFh
040h~07fh
000h-03Fh
040h-07Fh
080h-0BFh
mapping
address
;Set bank mapping 40h-07Fh to
0200h-023Fh
;Store #55H to A
;Write #55H to 0203h ;address
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
768 bytes SRAM
768 bytes SRAM
768 bytes SRAM
768 bytes SRAM
768 bytes SRAM
768 bytes SRAM
768 bytes SRAM
768 bytes SRAM
Lower 128 bytes
Lower 128 bytes
768 bytes SRAM
Upper 128 bytes
Upper 128 bytes
768 byte SRAM
768 byte SRAM
768 byte SRAM
SRAM
SRAM
SRAM
SRAM
Note
Description of Peripherals
System Control Register
The following table describes the System Control
Register (SYSCON).
The WDRESET bit (7) indicates whether a reset was
due to the Watchdog Timer overflow.
The IAPE bit is used to enable and disable the IAP
function.
When set to 1, the XRAME bit allows the user to
enable the on-chip expanded 768 bytes of SRAM. By
default, upon reset, the XRAME bit is set to 0.
Bit 0 of the SYSCON register is the ALE output inhibit
bit. Setting this bit to 1 will inhibit the Fosc/6 clock
signal output to the ALE pin.
T
ABLE
WDR
Bit
7
6
5
4
3
2
1
0
7
16: S
YSTEM
Mnemonic
WDR
Unused
Unused
Unused
Unused
IAPE
XRAME
ALEI
6
C
5
Unused
ONTROL
4
R
EGISTER
Description
This is the Watchdog Timer reset bit. It will
be set to 1 when the reset signal generated
by WDT overflows.
-
-
-
-
IAP function enable bit
768 bytes on-chip SRAM enable bit
ALE output inhibit bit, which is used to
reduce EMI.
3
(SYSCON) – SFR BF
IAPE
2
page 11 of 48
XRAME
H
1
ALEI
0