VRS51C1000-40-QG-ISPV2 Ramtron, VRS51C1000-40-QG-ISPV2 Datasheet - Page 13

• Manufacturer Part Number: VRS51C1000-40-QG-ISPV2
• Description: Microcontrollers (MCU) 64K+1K 40MHz 5V
• Manufacturer: Ramtron

Specifications of VRS51C1000-40-QG-ISPV2

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFP-44
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 128 B
• Height: 2 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 10 mm
• Lead Free Status / Rohs Status: Details

The transistor would be off (open-circuited) and current
would flow from the VCC to the pin, generating a
logical high at the output.
device with a logical low value is connected to the pin,
current will flow out of the pin.
The presence of the pull-up resistance even when the
I/O’s are configured as inputs means that a small
current is likely to flow from the VRS51C1000 I/O’s
pull-up resistors to the driving circuit when the inputs
are driven low. For this reason, the VRS51C1000 I/O
ports P1, P2, P3 and P4 are called “quasi bi-
directional”.
Structure of Port 0
The internal structure of P0 is shown in the next figure.
As opposed to the other ports, P0 is truly bi-directional.
In other words, when used as an input, it is considered
to be in a floating logical state (high impedance state).
This arises from the absence of the internal pull-up
resistance. The pull-up resistance is actually replaced
by a transistor that is only used when the port is
configured for accessing external memory/data bus
(EA=0).
When used as an I/O port, P0 acts as an open drain
port and the use of an external pull-up resistor is likely
to be required for most applications.
When P0 is used as an external memory bus input (for
a MOVX instruction, for example), the outputs of the
register are automatically forced to 1.
The bit addressable P0 register, located at address
80h, controls the P0 pin directions when used as I/O
(see following table).
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F
Internal Bus
IGURE
Write to
Register
VRS51C1000
Read Register
7: P
Read Pin
ORT
P0’
S PARTICULAR STRUCTURE
D Flip-Flop
Q
Q
Address A0/A7
Note that if an external
Control
Vcc
X1
IC Pin
T
Port 2
Port P2 is similar to Port 1 and Port 3, the difference
being that P2 is used to drive the A8-A15 lines of the
address bus when the EA line of the VRS51C1000 is
held low at reset time or when a MOVX instruction is
executed.
Like the P0, P1 and P3 registers, the P2 register is bit
addressable.
T
ABLE
ABLE
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
P0.7
P2.7
7
7
18: P
19: P
ORT
ORT
Mnemonic
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Mnemonic
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P0.6
P2.6
6
6
0 R
2 R
EGISTER
EGISTER
P0.5
P2.5
5
5
(P0) - SFR 80
(P2) - SFR A0
Description
For each bit of the P0 register correspond
to an I/O line:
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up brings the I/O to 5V.
Description
For each bit of the P2 register correspond
to an I/O line:
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up brings the I/O to 5V.
P0.4
P2.4
4
4
H
H
P0.3
P2.3
3
3
page 13 of 48
P0.2
P2.2
2
2
P0.1
P2.1
1
1
P0.0
P2.0
0
0