VRS51C1000-40-QG-ISPV2 Ramtron, VRS51C1000-40-QG-ISPV2 Datasheet - Page 9

• Manufacturer Part Number: VRS51C1000-40-QG-ISPV2
• Description: Microcontrollers (MCU) 64K+1K 40MHz 5V
• Manufacturer: Ramtron

Specifications of VRS51C1000-40-QG-ISPV2

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFP-44
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 128 B
• Height: 2 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 10 mm
• Lead Free Status / Rohs Status: Details

Program Status Word Register
The PSW register is a bit addressable register that
contains the status flags (CY, AC, OV, P), user flag
(F0) and register bank select bits (RS1, RS0) of the
8051 processor.
T
Data Pointer
The VRS51C1000 has one 16-bit data pointer. The
DPTR is accessed via two SFR addresses: DPL
located at address 82h and DPH located at address
83h.
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ABLE
Bit
7
6
5
4
3
2
1
0
RS1
VRS51C1000
CY
7
0
0
1
1
12: P
ROGRAM
Mnemonic
CY
AC
F0
RS1
RS0
OV
-
P
AC
6
RS0
0
1
0
1
S
TATUS
F0
5
W
Description
Carry Bit
Auxiliary Carry Bit from bit 3 to 4.
User definer flag
R0-R7 Registers bank select bit 0
R0-R7 Registers bank select bit 1
Overflow flag
-
Parity flag
ORD
RS1
4
Active Bank
R
EGISTER
RS0
0
1
2
3
3
(PSW) - SFR DO
OV
2
H
Address
00h-07h
08h-0Fh
10h-17h
18-1Fh
1
-
P
0
Data Memory
The VRS51C1000 has total of 1KB of on-chip SRAM
with a 256 byte subset of this block mapped as the
internal memory structure of a standard 8052. The
remaining 768 byte sub-block can be accessed using
external memory addressing via the MOVX instruction.
F
By default after reset, the expanded SRAM area is
disabled. It can be enabled by setting the XRAME bit
of the SYSCON register located at address BFh in the
SFR.
Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1)
The lower 128 bytes of data memory (from 00h to 7Fh)
can is summarized as follows:
Upper 128 bytes (80h to FFh, Bank 2 & Bank 3)
The upper 128 bytes of the data memory ranging from
80h to FFh can be accessed using indirect addressing
or by using the bank mapping in direct addressing
mode.
Stack Pointer
The Stack Pointer is a register located at address 81h
of the SFR register area whose value corresponds to
the address of the last item that was put on the
processor stack. Each time new data is put on the
Stack Pointer, the value of the Stack Pointer is
incremented.
By default, the Stack Pointer value is 07h, but it is
possible to program the processor stack pointer to
IGURE
FF
80
7F
00
o
o
o
o
5: VRS51C1000 D
(Indirect addressing mode only)
Address range 00h to 7Fh can be accessed in
direct and indirect addressing modes.
Address range 00h to 1Fh includes R0-R7
registers area.
Address range 20h to 2Fh is bit addressable.
Address range 30h to 7Fh is not bit
addressable and can be used as general-
purpose storage.
Upper 128 bytes
Lower 128 bytes
ATA
M
EMORY
(Direct addressing mode only)
SFR
page 9 of 48
external addressing mode,
Expanded 768 bytes
(accessed by direct
using the MOVX
(XRAME=1)
instruction)
02FF
0000