74HC4852PW,118 NXP Semiconductors, 74HC4852PW,118 Datasheet

IC MUX/DEMUX DUAL 4X1 16TSSOP

74HC4852PW,118

Manufacturer Part Number
74HC4852PW,118
Description
IC MUX/DEMUX DUAL 4X1 16TSSOP
Manufacturer
NXP Semiconductors
Series
74HCr
Type
Analog Multiplexerr
Datasheets

Specifications of 74HC4852PW,118

Package / Case
16-TSSOP (0.173", 4.40mm Width)
Function
Multiplexer/Demultiplexer
Circuit
2 x 4:1
On-state Resistance
59 Ohm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
2 V ~ 6 V
Current - Supply
2µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Channels
2 Channel
On Resistance (max)
650 Ohm @ 2 V
On Time (max)
47.5 ns @ 2 V
Off Time (max)
100 ns @ 2 V
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Switches
Dual
Package
16TSSOP
Maximum On Resistance
650@2V Ohm
Maximum Propagation Delay Bus To Bus
38@2V|20@3V|17.5@3.3V|14@4.5V|12.6@6V ns
Maximum Low Level Output Current
25 mA
Multiplexer Architecture
4:1
Maximum Turn-off Time
100@2V ns
Maximum Turn-on Time
47.5@2V ns
Power Supply Type
Single
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74HC4852PW-T
74HC4852PW-T
935282089118

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74HC4852PW,118
Manufacturer:
TexasInstruments
Quantity:
285
1. General description
2. Features
The 74HC4852; 74HCT4852 are high-speed Si-gate CMOS devices and are specified in
compliance with JEDEC standard no. 7A.
The 74HC4852; 74HCT4852 are dual 4-channel analog multiplexers/demultiplexers with
common select inputs (S0 and S1). Both multiplexers have a common active LOW enable
input (E), four independent inputs/outputs (nY0 to nY3) and two common inputs/outputs
(1Z, 2Z). The devices feature injection-current effect control, which has excellent value in
automotive applications where voltages in excess of the supply voltage are common.
With E LOW, two of the eight switches are selected (low impedance ON-state) by S0 and
S1. With E HIGH, all switches are in the high-impedance OFF-state, independent of S0
and S1.
The injection-current effect control allows signals at disabled analog input channels to
exceed the supply voltage without affecting the signal of the enabled analog channel. This
eliminates the need for external diode/resistor networks typically used to keep the analog
channel signals within the supply-voltage range.
I
I
I
I
I
74HC4852; 74HCT4852
Dual 4-channel analog multiplexer/demultiplexer with
injection-current effect control
Rev. 03 — 2 September 2008
Injection-current cross coupling < 1 mV/mA
Wide supply voltage range from 2.0 V to 6.0 V for 74HC4852
ESD protection:
Latch-up performance exceeds 100 mA per JESD 78 Class II level A
Low ON-state resistance:
N
N
N
N
N
N
N
HBM JESD22-A114E exceeds 2000 V
CDM JESD22-C101C exceeds 1000 V
400
215
120
76
59
(typical) at V
(typical) at V
(typical) at V
(typical) at V
(typical) at V
CC
CC
CC
CC
CC
= 4.5 V
= 6.0 V
= 2.0 V
= 3.0 V
= 3.3 V
Product data sheet

Related parts for 74HC4852PW,118

74HC4852PW,118 Summary of contents

Page 1

Dual 4-channel analog multiplexer/demultiplexer with injection-current effect control Rev. 03 — 2 September 2008 1. General description The 74HC4852; 74HCT4852 are high-speed Si-gate CMOS devices and are specified in compliance with JEDEC standard no. 7A. The 74HC4852; 74HCT4852 ...

Page 2

... NXP Semiconductors 3. Applications I Analog multiplexing and demultiplexing I Digital multiplexing and demultiplexing I Signal gating I Automotive application 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC4852D +125 C 74HC4852PW +125 C 74HC4852BQ +125 C 74HCT4852D +125 C 74HCT4852PW +125 C 74HCT4852BQ +125 C 5. Functional diagram ...

Page 3

... NXP Semiconductors Fig 3. Functional diagram 74HC_HCT4852_3 Product data sheet 74HC4852; 74HCT4852 4-channel analog MUX/DEMUX with injection-current effect control 1-OF-4 DECODER GND 8 Rev. 03 — 2 September 2008 INJECTION 13 1Z CURRENT CONTROL INJECTION 12 1Y0 CURRENT CONTROL INJECTION 14 1Y1 CURRENT CONTROL INJECTION 15 1Y2 CURRENT CONTROL ...

Page 4

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74HC4852 74HCT4852 2Y0 1 2 2Y2 2Z 3 2Y3 4 5 2Y1 GND 001aag096 Fig 4. Pin configuration SO16 and TSSOP16 6.2 Pin description Table 2. Pin description Symbol Pin 2Y0 1 2Y2 2Y3 4 2Y1 n.c. 7 GND 1Y3 11 1Y0 ...

Page 5

... NXP Semiconductors 7. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage ...

Page 6

... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); For test circuit see ...

Page 7

... NXP Semiconductors Table 7. Injection current coupling At recommended operating conditions; voltages are referenced to GND (ground 0 V); For test circuit see Symbol Parameter +125 C amb V output voltage O variation [1] Typical values are measured at T [2] V here is the maximum variation of output voltage of an enabled analog channel when current is injected into any disabled channel. ...

Page 8

... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions I OFF-state S(OFF) IH leakage current V; see Figure 6 nYn; per channel nZ; all channels I ON-state S(ON) IL leakage current V; see Figure 7 I supply V = GND current input S0, S1, S2 and E ...

Page 9

... NXP Semiconductors nYn I S GND V I Fig 6. Test circuit for measuring OFF-state leakage current nYn GND Fig 8. Test circuit for measuring ON resistance 74HC_HCT4852_3 Product data sheet 74HC4852; 74HCT4852 4-channel analog MUX/DEMUX with injection-current effect control 001aag098 (1) Channel is selected by S0 and S1. ...

Page 10

... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V); for load circuit see Symbol Parameter Conditions 74HC4852 t propagation delay nZ, nYn to nYn, nZ; pd see Sn to nZ, nYn; see t enable time E to nZ, nYn; en see t disable time E to nZ, nYn; ...

Page 11

... NXP Semiconductors Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V); for load circuit see Symbol Parameter Conditions 74HCT4852 t propagation delay nZ, nYn to nYn, nZ; pd see nZ, nYn; see V t enable time E to nZ, nYn; en see V t disable time E to nZ, nYn; ...

Page 12

... NXP Semiconductors nYn or nZ Measurement points are given in Fig 11. Input (Sn) to output (nYn, nZ) propagation delays nZ or nYn output nZ or nYn output Measurement points are shown in Logic levels: V and Fig 12. Enable and disable times Table 10. Measurement points Type Input V M 74HC4852 0.5V ...

Page 13

... NXP Semiconductors Fig 13. Test circuit for measuring power dissipation capacitance 74HC_HCT4852_3 Product data sheet 74HC4852; 74HCT4852 4-channel analog MUX/DEMUX with injection-current effect control selected channel nYn n.c. E nYn disabled channel GND 001aah581 Rev. 03 — 2 September 2008 © NXP B.V. 2008. All rights reserved. ...

Page 14

... NXP Semiconductors a. Input pulse definition Definitions for test circuit load resistance load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Load circuit Test data is given in Table 11. Fig 14. Input pulse definition and load circuit Table 11. Test data ...

Page 15

... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 16

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 17

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 18

... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date 74HC_HCT4852_3 20080902 • Modifications: 74HCT4852 device added ...

Page 19

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 20

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Abbreviations ...

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