AC101LKQT Broadcom, AC101LKQT Datasheet - Page 11

• Manufacturer Part Number: AC101LKQT
• Manufacturer: Broadcom

Specifications of AC101LKQT

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Not Compliant

03/10/03
P
Because there are many devices in the field that do not support the ANEN process, but must still be communicated with, it
is necessary to detect and link through the parallel detection process. The parallel detection circuit is enabled in the absence
of FLPs. The circuit is able to detect the following:
•
•
•
The mode of operation gets configured based on the technology of the incoming signal. If any of the above is detected, the
device automatically configures to match the detected operating speed in the half-duplex mode. This ability allows the device
to communicate with the legacy 10BASE-T and 100BASE-TX systems, while maintaining the flexibility of auto-negotiation.
A
The analog adaptive equalizer removes Inter Symbol Interference (ISI) created by the transmission channel media.
The PHY is designed to accommodate a maximum of 140 meters of UTP Category 5 cable. An AT&T 1061 Category 5 cable
of this length typically has an attenuation of 31 dB at 100 MHz. A typical attenuation of 100-meter cable is 21 dB. The worst
case cable attenuation is around 24–26 dB as defined by TP-PMD specification. The amplitude and phase distortion from
the cable causes ISI which makes clock and data recovery difficult. The adaptive equalizer is designed to closely match the
inverse transfer function of the twisted-pair cable. The equalizer has the ability to changes its equalizer frequency response
according to the cable length. The equalizer will tune itself automatically for any cable, compensating for the amplitude and
phase distortion introduced by the cable.
C
The equalized MLT3 signal passes through the slicer circuit, and gets converted to NRZI format. The PHY uses a proprietary
mixed-signal Phase Locked Loop (PLL) to extract clock information from the incoming NRZI data. The extracted clock is
used to re-time the data stream and set the data boundaries. The transmit clock is locked to the 25 MHz clock input while
the receive clock is locked to the incoming data streams. When initial lock is achieved, the PLL switches to the data stream,
extracts the 125 MHz clock, and uses it for the bit framing for the recovered data. The recovered 125 MHz clock is also used
to generate the 25 MHz RX_CLK signal. The PLL requires no external components for its operation and has high noise
immunity and low jitter. It provides fast phase alignment and locks to data in one transition. Its data/clock acquisition time,
after power-on, is less than 60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of
signal transitions. When no valid data is present (that is, when the SD is deasserted), the PLL switches and locks on to
Document
4.7/1.13
4.6/1.12
4.5/1.11
ARALLEL
NALOG
LOCK
Normal link pulse (NLP)
10BASE-T receive data
100BASE-TX idle
AC101L-DS05-R
R
A
ECOVERY
100BASE-TX
10BASE-T Full-Duplex
10BASE-T
DAPTIVE
D
ETECTION
E
QUALIZER
The default value is:
SPD100 && (ANEN || !DUPLEX)
The default value of this bit is:
DUPLEX && (ANEN || !SPD100)
The default value is:
ANEN || (!SPD100 && !DUPLEX)
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