AC101LKQT Broadcom, AC101LKQT Datasheet - Page 16

• Manufacturer Part Number: AC101LKQT
• Manufacturer: Broadcom

Specifications of AC101LKQT

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Not Compliant

AC101L
Page
PIN #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
8
PIN name
REPEATER/ CRS
GND
VCC
PHYAD0/INTR
BURNIN/LED0
SPD100/LED1
DUPLEX/LED2
ANEN/LED3
PDOWN
VCC
RXN
RXP
SD/FXEN
GND
GND
RBIAD
VCCPLL
GND
TXN
TXP
VCC25OUT
GND
GND
XO
XI
VCC33IN
P
Type
B
G
P
B
B
B
B
B
B
P
A
A
AI
G
G
A
P
G
A
A
P
G
G
A
A
D
U
U
U
U
U
U
Table 1: Pinout and Signal Definitions
Description
REPEATER: Resets read input. Active high puts the chip in repeater mode.
CRS (active HIGH output): Carrier sense signal in the MII interface. CRS is asserted
when the twisted-pair media is non-idle and is deasserted when idle or a valid end-of-
stream delimiter is detected.
Ground
+2.5 V power supply.
PHYAD0: Resets read input. Pull high or low to set the PHY Address bit 0 for the MII
management function.
INTR (output): interrupt output enable. The active value is the inverse of its reset read
value.
BURNIN: Resets read input. Set Active LOW to put the chip in burn-in test mode.
LED0 (output): Low active, the default behavior is ON when the chip is in link-up
condition and is BLINK when the chip detects transmits or receive activity.
SPD100: Resets read input.
If ANEN is Low, SPD100 sets the TP port speed in register 0.
If ANEN is High, SPD100 is used to set 100 Mbps half-duplex and 100 Mbps full-duplex
bits in register 4.
LED1 (output): Low active. The default behavior is ON when the chip is operating at 100
Mbps, and is OFF when the chip is operating at 10 Mbps.
DUPLEX: Resets read input.
If ANEN is Low, DUPLEX sets the TP port in full-duplex mode in register 0.
If ANEN is High, DUPLEX is used to set 10 Mbps FDX and 100 Mbps FDX bits in
register 4.
LED2 (output): Low active. The default behavior is ON when the chip is operating in full-
duplex mode and is OFF when the chip is operating in half-duplex mode.
ANEN (resets read input): Auto-negotiation enable for the twisted-pair port. Pull high to
enable auto-negotiation. Pull low to disable auto-negotiation.
LED3 (output): Low active. The default behavior is BLINK when the chip detect collision
is in half-duplex mode.
PDOWN (input): Power-down input. This pin must be pulled high externally for normal
operation. Pulling this pin low puts both the TP and fiber port into power-down mode.
This is a regular input, not a reset read signal.
+2.5 V power supply.
Receive. For TP port in MDI mode.
Transmit. For TP port in MDIX mode.
Receive +. For TP port in MDI mode.
Transmit +. For TP port in MDIX mode.
SD/FXEN (analog input): This pin must be pulled low externally for normal TP mode.
Connect to fiber module to enable FX mode; also serves as signal detect input.
Ground
Ground
Bias resistor connection. Connect to a 10K 1% resistor to GND.
+2.5 V supply for analog bias, PLL modules.
Ground
Transmit. In MDI mode.
Receive. In MDIX mode.
Transmit +. In MDI mode.
Receive +. In MDIX mode.
+2.5 VCC out from the on chip regulator.
Ground
Ground
XTAL output.
XTAL input.
In MII Mode: XI and XO is designed to connect to a 25 MHz., 50 PPM XTAL or 25 MHz
OSC.
3.3 V Power supply input.
B roa dcom
(Cont.)
Preliminary Data Sheet
Document
AC101L-DS05-R
03/10/03