AC101LKQT Broadcom, AC101LKQT Datasheet - Page 21

• Manufacturer Part Number: AC101LKQT
• Manufacturer: Broadcom

Specifications of AC101LKQT

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Not Compliant

03/10/03
R
The PHY can be reset in three ways:
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•
•
P
The AC101L chip provides an onboard 3.3 V ±5% input to 2.5 V ±5% output regulator with the capability to drive 150 mA of
current. The 2.5 V output supplies the PHY operation, including the LEDs. It is recommended to limit the LED current below
10 mA per LED.
The 2.5 V power should be decoupled to provide the digital and analog pins on the chip.
P
The power consumption of the AC101L device is significantly reduced due to its built-in power management features.
Separate power supply lines are used to power the 10BASE-T circuitry and the 100BASE-TX circuitry. Therefore, the two
circuits can be turned on and turned off independently. When the PHY is set to operate in 100BASE-TX mode, the 10BASE-
T circuitry is powered down.
The following power management features are supported:
•
•
•
Document
OWER
OWER
ESET
During initial power on.
Hardware reset: (See
Software reset: (See
Power-down mode: (see pin and register descriptions). During power down mode, the device is still able to interface
through the management interface.
Energy detect/power saving mode: Energy detect mode turns off the power to select internal circuitry when there is
no live network connected. The energy detect (ED) circuit is always turned on to monitor if there is signal energy
present on the media. The management circuitry is also powered on and ready to respond to any management
transaction. The transmit circuit still sends out link pulses with minimum power consumption. If a valid signal is received
from the media, the device powers up and resumes normal transmit/receive operations.
Valid data detection mode: This can be achieved by writing to the Receive Clock Register control bit. During this
mode, if there is no data other than incoming idles, the receive clock (RX_CLK) turns itself off. This could save the
power of the attached media access controller. RX_CLK resumes operation one clock period prior to the assertion of
RXDV. The receive clock again shuts off 64 clock cycles after RXDV is deasserted.
AC101L-DS05-R
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S ec t io n 4 : O pe rat i o na l De scr ip t io n
“Register Description” on page
“Pin Descriptions” on page
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