CY7C25702KV18-550BZXI Cypress Semiconductor Corp, CY7C25702KV18-550BZXI Datasheet - Page 10

• Manufacturer Part Number: CY7C25702KV18-550BZXI
• Description: IC SRAM DDR-II+ CIO-ODT 165FBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C25702KV18-550BZXI

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Echo Clocks
Echo clocks are provided on the DDR II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free-running clocks and are
synchronized to the input clock of the DDR II+. The timing for the
echo clocks is shown in the
page 24.
Valid Data Indicator (QVLD)
QVLD is provided on the DDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
On-Die Termination (ODT)
These devices have an On-Die Termination feature for Data
inputs (D
and K). The termination resistors are integrated within the chip.
The ODT range selection is enabled through ball R6 (ODT pin).
The ODT termination tracks value of RQ where RQ is the resistor
tied to the ZQ pin. ODT range selection is made during power up
Application Example
Figure 1
Figure 1. Application Example
Document Number: 001-66483 Rev. **
(CPU or ASIC)
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
shows two DDR II+ used in an application.
MASTER
[x:0]
BUS
), Byte Write Selects (BWS
Source CLK
Source CLK
Addresses
BWS
ODT
R/W
DQ
LD
“Switching Characteristics”
DQ
[x:0]
A
), and Input Clocks (K
LD
SRAM#1
R/W BWS
CQ/CQ
K
ODT
on
ZQ
K
R = 250ohms
initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175< RQ < 350(where RQ is the resistor tied to
ZQ pin) A HIGH on this pin selects a high range that follows
RQ/1.66 for 175< RQ < 250(where RQ is the resistor tied to
ZQ pin). When left floating, a high range termination value is
selected by default. For a detailed description on the ODT imple-
mentation, refer to the application note, On-Die Termination for
QDRII+/DDRII+ SRAMs.
PLL
These chips use a PLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the PLL is locked after 20 s
of stable clock. The PLL can also be reset by slowing or stopping
the input clock K and K for a minimum of 30 ns. However, it is not
necessary to reset the PLL to lock to the desired frequency. The
PLL automatically locks 20 s after a stable clock is presented.
The PLL may be disabled by applying ground to the DOFF pin.
When the PLL is turned off, the device behaves in DDR I mode
(with one cycle latency and a longer access time). For infor-
mation, refer to the application note, PLL Considerations in
QDRII/DDRII/QDRII+/DDRII+.
CY7C25662KV18, CY7C25772KV18
CY7C25682KV18, CY7C25702KV18
DQ
A
LD
SRAM#2
R/W BWS
CQ/CQ
K
ODT
ZQ
K
R = 250ohms
Page 10 of 29
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