CY7C25702KV18-550BZXI Cypress Semiconductor Corp, CY7C25702KV18-550BZXI Datasheet - Page 11

• Manufacturer Part Number: CY7C25702KV18-550BZXI
• Description: IC SRAM DDR-II+ CIO-ODT 165FBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C25702KV18-550BZXI

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Truth Table
The truth table for the CY7C25662KV18, CY7C25772KV18, CY7C25682KV18, and CY7C25702KV18 follow.
Write Cycle Descriptions
The write cycle description table for CY7C25662KV18 and CY7C25682KV18 follows.
Document Number: 001-66483 Rev. **
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read Cycle: (2.5 cycle Latency)
Load address; wait two and half cycles;
read data on consecutive K and K rising edges.
NOP: No Operation
Standby: Clock Stopped
Notes
BWS
NWS
4. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, 
5. Device powers up deselected with the outputs in a tri-state condition.
6. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
7. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
9. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically
10. Is based on a write cycle that was initiated in accordance with
H
H
H
H
L
L
L
L
cycle, as long as the setup and hold requirements are achieved.
0
0
/
BWS
NWS
H
H
H
H
L
L
L
L
1
1
/
L–H
L–H
L–H
L–H
K
–
–
–
–
Operation
L–H During the data portion of a write sequence
L–H During the data portion of a write sequence
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence
K
–
–
–
–
During the data portion of a write sequence
CY7C25662KV18 both nibbles (D
CY7C25682KV18 both bytes (D
CY7C25662KV18 both nibbles (D
CY7C25682KV18 both bytes (D
During the data portion of a write sequence
CY7C25662KV18 only the lower nibble (D
CY7C25682KV18 only the lower byte (D
CY7C25662KV18 only the lower nibble (D
CY7C25682KV18 only the lower byte (D
During the data portion of a write sequence
CY7C25662KV18 only the upper nibble (D
CY7C25682KV18 only the upper byte (D
CY7C25662KV18 only the upper nibble (D
CY7C25682KV18 only the upper byte (D
No data is written into the devices during this portion of a write operation.

represents rising edge.
Table
. NWS
Stopped
L-H
L-H
L-H
K
0
, NWS
[17:0]
[17:0]
[7:0]
[7:0]
1
, BWS
) are written into the device.
) are written into the device.
) are written into the device.
) are written into the device.
LD
H
X
CY7C25662KV18, CY7C25772KV18
CY7C25682KV18, CY7C25702KV18
L
L
[8:0]
[8:0]
[17:9]
[17:9]
0
, BWS
[3:0]
[3:0]
Comments
[7:4]
[7:4]
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
1
, BWS
R/W
H
X
X
L
2
[4, 10]
, and BWS
D(A) at K(t + 1) 
Q(A) at K(t + 2)
High Z
Previous State
3
can be altered on different portions of a write
DQ
[17:9]
[17:9]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
[4, 5, 6, 7, 8, 9]
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
D(A+1) at K(t + 1) 
Q(A+1) at K(t + 3) 
High Z
Previous State
Page 11 of 29
DQ
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