CY7C25702KV18-550BZXI Cypress Semiconductor Corp, CY7C25702KV18-550BZXI Datasheet - Page 8

• Manufacturer Part Number: CY7C25702KV18-550BZXI
• Description: IC SRAM DDR-II+ CIO-ODT 165FBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C25702KV18-550BZXI

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 2. Pin Definitions (continued)
Document Number: 001-66483 Rev. **
Pin Name
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/144M
NC/288M
V
V
V
V
REF
DD
SS
DDQ
Power Supply Power Supply Inputs to the Core of the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Echo Clock
Echo Clock
Reference
Ground
Output
Input-
Input
Input
Input
Input
Input
Input
Input
N/A
I/O
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
PLL Turn Off  Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in DDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Ground for the Device.
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
Pin Description
CY7C25662KV18, CY7C25772KV18
CY7C25682KV18, CY7C25702KV18
Switching Characteristics
Switching Characteristics
DDQ
, which enables the
Page 8 of 29
on page 24.
on page 24.
[+] Feedback