LM3208TL/NOPBPB National Semiconductor, LM3208TL/NOPBPB Datasheet - Page 16

• Manufacturer Part Number: LM3208TL/NOPBPB
• Manufacturer: National Semiconductor

Specifications of LM3208TL/NOPBPB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

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Application Information
The LM3208 converts higher input voltage to lower output
voltage with high efficiency. This is achieved with an
inductor-based switching topology. During the first half of the
switching cycle, the internal PMOS switch turns on, the input
voltage is applied to the inductor, and the current flows from
PV
inductor. During the second half cycle, the PMOS turns off
and the internal NMOS turns on. The inductor current con-
tinues to flow via the inductor from the device PGND line into
the output capacitor and the load.
Referring to Figure 4, a pulse current flows in the left hand
side loop, and a ripple current flows in the right hand side
loop. Board layout and circuit pattern design of these two
loops are the key factors for reducing noise radiation and
stable operation. In other lines, such as from battery to C1
and C2 to the load, the current is mostly DC current. There-
fore, it is not necessary to take so much care. Only pattern
width (current capability) and DCR drop considerations are
needed.
IN
line into the output capacitor and the load through the
FIGURE 5. Evaluation Board Layout
(Continued)
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16
BOARD LAYOUT FLOW
1. Minimize C1, PV
2. Minimize L1, C2, SW and PGND loop. These traces also
3. The above layout patterns should be placed on the
4. Connect C1(-), C2(-) and PGND with wide GND pattern.
5. SGND should not connect directly to PGND. Connecting
6. V
7. The FB line should be protected from noise. It is a good
Note: The evaluation board shown in Figure 5 for the LM3208 was designed
should be as wide and short as possible. This is the
highest priority.
should be wide and short. This is the second priority.
component side of the PCB to minimize parasitic induc-
tance and resistance due to via-holes. It may be a good
idea that the SW to L1 path is routed between C1(+) and
C1(-) land patterns. If vias are used in these large cur-
rent paths, multiple via-holes should be used if possible.
This pattern should be short, so C1(-), C2(-), and PGND
should be as close as possible. Then connect to a PCB
common GND pattern with as many via-holes as pos-
sible.
these pins under the device should be avoided. (If pos-
sible, connect SGND to the common port of C1(-), C2(-)
and PGND.)
ing these pins under the device should be avoided. It is
good idea to connect V
noise injection to the V
idea to use an inner GND layer (if available) as a shield.
with these considerations, and it shows good performance. However
some aspects have not been optimized because of limitations due to
evaluation-specific requirements. The board can be used as a refer-
ence. Please refer questions to a National representative.
DD
should not be connected directly to PV
IN
, and PGND loop. These traces
DD
DD
line.
to C1(+) to avoid switching
IN
. Connect-