LFE3-35EA-8FN672I Lattice, LFE3-35EA-8FN672I Datasheet - Page 27

IC FPGA 33.3K LUTS 310I/O FN672

LFE3-35EA-8FN672I

Manufacturer Part Number
LFE3-35EA-8FN672I
Description
IC FPGA 33.3K LUTS 310I/O FN672
Manufacturer
Lattice
Series
ECP3r

Specifications of LFE3-35EA-8FN672I

Number Of Logic Elements/cells
33000
Number Of Labs/clbs
4125
Total Ram Bits
1358848
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1163
Lattice Semiconductor
For further information, please refer to TN1182,
MULT DSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, AA and
AB, are multiplied and the result is available at the output. The user can enable the input/output and pipeline regis-
ters. Figure 2-26 shows the MULT sysDSP element.
Figure 2-26. MULT sysDSP Element
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
IR
C
IR
AA
MULTA
PR
OR
AMUX
A_ALU
IR
From FPGA Core
LatticeECP3 sysDSP Usage
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-24
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
LatticeECP3 Family Data Sheet
OR
PR
Guide.
IR
BB
IR
COUT
SROB
SROA
DSP Slice
Next
Architecture

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