LFXP3E-5TN100C Lattice, LFXP3E-5TN100C Datasheet - Page 336

• Manufacturer Part Number: LFXP3E-5TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-5TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
sis Library. The definitions of these library elements can be found in the Reference Manuals section of the isp-
LEVER on-line help system.
IPepxress, a parameterized module complier optimized for Lattice FPGA devices, is available for more complex
logic functions. IPexpress supports generation of library elements with a number of different options such as PLLs
and creates parameterized logic functions such as PFU and EBR memory, multipliers, adders, subtractors, and
counters. IPexpress accepts options that specify parameters for parameterized modules such as data path mod-
ules and memory modules, and produces a circuit description with Lattice Semiconductor FPGA library elements.
Output from IPexpress can be written in EDIF, VHDL, or Verilog. In order to use synthesis tools to utilize the Lattice
FPGA architectural features, it is strongly recommended to use IPexpress to generate modules for source code
instantiation. The following are examples of Lattice Semiconductor FPGA modules supported by IPexpress:
IPexpress is especially efficient when generating high pin count modules as it saves time in manually cascading
small library elements from the synthesis library. Detailed information about IPexpress and its user guide can be
found in the ispLEVER help system.
• Logic gates and LUTs
• Comparators, adders, subtractors
• Counters
• Flip-flops and latches
• Memory, 4E-specific memory (block RAM function)
• Multiplexors
• Multipliers
• All I/O cells, including I/O flip-flops
• PIC cells
• Special cells, including PLL, GSR, boundary scan, etc.
• FPSC elements
• PLL
• Memory implemented in PFU:
• Memory implemented with EBR:
• Other EBR based Functions
• PFU based functions
• MPI/System Bus
– Synchronous single-port RAM, synchronous dual-port RAM, synchronous ROM, synchronous FIFO
– Quad-port Block RAM, Dual-Port Block RAM, Single-Port Block RAM, ROM, FIFO
– Multiplier, CAM
– Multiplier, adder, subtractor, adder/subtractor, linear feedback shifter, counter
13-9
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs