LFE2-50E-7FN484C Lattice, LFE2-50E-7FN484C Datasheet - Page 23
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LFE2-50E-7FN484C
Manufacturer Part Number
LFE2-50E-7FN484C
Description
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-7FN484C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 2-20. Memory Core Reset
For further information about the sysMEM EBR block, please see the the list of additional technical documentation
at the end of this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-21. The GSR input to the
EBR is always asynchronous.
Figure 2-21. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becomes active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
sysDSP™ Block
The LatticeECP2/M family provides a sysDSP block, making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-20
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeECP2/M Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture
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