LFE2-50E-7FN484C Lattice, LFE2-50E-7FN484C Datasheet - Page 26
LFE2-50E-7FN484C
Manufacturer Part Number
LFE2-50E-7FN484C
Description
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-7FN484C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Lattice Semiconductor
MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers, but the out-
put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in the LatticeECP2/M family can be initialized dynamically. A registered overflow signal is also avail-
able. The overflow conditions are provided later in this document. Figure 2-24 shows the MAC sysDSP element.
Figure 2-24. MAC sysDSP
Multiplicand
Multiplier
Signed A
Signed B
Addn
Accumsload
Serial Register B in
n
Register B
Input Data
n
n
SROB
n
Register
Register
Register
Register
Input
Input
Input
Input
m
Input Data
Register A
m
n
SROA
Serial Register A in
m
Register
Register
Register
Register
Pipeline
Pipeline
Pipeline
Pipeline
m
n
2-23
To Accumulator
To Accumulator
To Accumulator
To Accumulator
Multiplier
Pipeline
Register
x
(default)
m+n
LatticeECP2/M Family Data Sheet
Accumulator
CLK (CLK0,CLK1,CLK2,CLK3)
RST(RST0,RST1,RST2,RST3)
CE (CE0,CE1,CE2,CE3)
(default)
m+n+16
Preload
(default)
m+n+16
Architecture
Output
Overflow
signal
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