MT46H4M32LFB5-5:K TR Micron Technology Inc, MT46H4M32LFB5-5:K TR Datasheet - Page 56

• Manufacturer Part Number: MT46H4M32LFB5-5:K TR
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H4M32LFB5-5:K TR

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 110mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 21: Status Register Definition
PDF: 09005aef8331b3e9
128mb_mobile_ddr_sdram_t35m.pdf - Rev. F 03/10 EN
S12
0
1
S10 S9
0
0
0
0
1
1
1
1
S15 S14
0
0
0
0
1
1
1
1
Device Type
LPDDR2
LPDDR
Reserved
0
0
1
1
0
0
1
1
DQ31...DQ16
31..16
S31..S16
0
1
1
0
0
1
1
0
S8
0
1
0
1
0
1
0
1
S13
0
1
0
1
0
1
0
1
1
Refresh Multiplier
Reserved
0.25X
Reserved
2X
1X
Reserved
Reserved
Notes:
Reserved
15
Density
DQ15
128Mb
256Mb
512Mb
1Gb
2GB
Reserved
Reserved
Reserved
S15
Density
14
DQ14
S14
S11
0
1
1. Reserved bits should be set to 0 for future compatibility.
2. Refresh multiplier is based on the memory device on-board temperature sensor. Re-
DQ13
S13
13
quired average periodic refresh interval =
Device Width
32 bits
16 bits
Type
12
DQ12
S12
2
Width
DQ11
11
S11
Refresh Rate
S7
...
0
X
DQ10
10
S10
S6
...
0
X
DQ9
9
S9
S5
...
0
X
DQ8
8
S8
S4
...
0
X
DQ7
7
56
S7
Revision ID
Revision ID
The manufacturer’s revision number starts at ‘0000’
and increments by ‘0001’ each time a change in the
specification (AC timings or feature set), IBIS (pull-
up or pull-down characteristics), or process occurs.
DQ6
6
S6
128Mb: x16, x32 Mobile LPDDR SDRAM
DQ5
5
S5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DQ4
S3
4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S4
t
Manufacturer ID
REFI × multiplier.
DQ3
S2
3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S3
S1
DQ2
2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S2
S0
DQ1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S1
Reserved
Reserved
Reserved
Reserved
Infineon
Elpida
Reserved
Reserved
Reserved
Winbond
ESMT
NVM
Reserved
Reserved
Micron
DQ0
Manufacturer ID
Samsung
0
S0
Status Read Register
© 2007 Micron Technology, Inc. All rights reserved.
I/O bus (CLK L->H edge)
Status register