UFX7000-VE Standard Microsystems (SMSC), UFX7000-VE Datasheet - Page 4

• Manufacturer Part Number: UFX7000-VE
• Description: USB 3.0 SUPER SPEED GRAPHICS CONTROLLER
• Manufacturer: Standard Microsystems (SMSC)

USB GRAPHICS ADAPTER
DDR2 SDRAM INTERFACE
PERIPHERALS
Revision 1.0 (12-16-10)
The USB Graphics Adapter consists of the following main blocks: the Graphics Engine, Display
Controller, HDMI/DVI Controller/PHY, Video DAC, and the Digital RGB Interface. Together, these
blocks support high definition resolutions of up to 2048x1152 (QWXGA) with 32-bit true color in both
standard and wide screen aspect ratios. The HDMI/DVI interface is compliant with the HDMI v1.3 and
DVI v1.0 specifications and supports 2-channel uncompressed PCM audio via a S/PDIF or I
The Display Controller also supports 8-bit and 16-bit color, gamma correction, Color Look-Up Table
(CLUT) and triple-buffered animation. The DDC2B/EDID VESA standard is supported, allowing the
host OS and device drivers to query the monitor’s frequency, resolution, and other features for true
plug-and-play and intelligent mode setting capabilities.
Once the graphics data has been received via the USB Bulk-Out Controller, it is sent to the Graphics
Engine. If the data is compressed, the Graphics Engine decompresses it via algorithms that have been
optimized for speed and quality. The device’s decompression algorithms have been designed to work
seamlessly with the compression algorithms utilized in the software device drivers.
The graphics data is then transferred to the SDRAM via the DDR2 SDRAM Controller. The Display
Controller generates all display and interface timing signals, retrieves the graphics data from the DDR2
SDRAM, and sends it to the HDMI/DVI Controller/PHY, Video DAC, or Digital RGB Interface.
The Digital RGB Interface may be used to connect external display interface IC’s (e.g., DisplayPort,
etc.) via the provided RGB data channel busses and control signals. The Digital RGB Interface
supports two modes of operation: 24-bit single data rate mode and 12/15-bit double data rate mode.
24-bit mode is single edge triggered and utilizes the full 24-bit data bus width. The 12/15-bit mode is
triggered on both clock edges and utilizes 12/15-bits of the data bus width.
The UFX7000 provides a full JEDEC compliant (JESD79-2E) DDR2 SDRAM Controller and PHY for
interfacing to external DDR2 SDRAM. The DDR2 SDRAM interface is comprised of JEDEC standard
1.8V I/O signals grouped into control signals, a 16-bit data bus, and a 13-bit address bus.
The DDR2 SDRAM Controller transfers the graphics data in and out of external SDRAM through the
DDR2 SDRAM PHY. External SDRAM is used as storage for the graphics and acts a a buffer between
the Graphics Engine and Display Controller.
The UFX7000 also contains an EEPROM Controller, I
The EEPROM Controller allows connection to an external EEPROM for automatic loading of static
configuration data upon power-on, pin reset, or software reset. The EEPROM can be configured to
load USB descriptors and USB device configuration.
The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
USB 3.0 Super-Speed Graphics Controller with VGA, HDMI/DVI, and Digital RGB Interfaces
PRODUCT PREVIEW
4
2
C Controller, and TAP Controller.
SMSC UFX7000
2
S input.