SL72P4M128M8M-B05AYU STEC, SL72P4M128M8M-B05AYU Datasheet - Page 13

• Manufacturer Part Number: SL72P4M128M8M-B05AYU
• Manufacturer: STEC

Specifications of SL72P4M128M8M-B05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 9Gb
• Access Time (max): 600ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 4.77A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P4M128M8M-B05AY(W)U
NOTES
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC
3. Outputs measured with equivalent load:
4. AC timing and IDD tests may use a VIL-to-VIH swing of
5. The AC and DC input level specifications are as defined in
6. Command/Address minimum input slew rate is at 1.0V/ns.
7. Data minimum input slew rate is at 1.0V/ns. Data input
characteristics may be conducted at nominal reference
supply voltage levels, but the related specifications and
device operation are guaranteed for the full voltage range
specified.
up to 1.0V in the test environment and parameter
specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 1.0V/
ns for signals in the range between VIL (AC) and VIH (AC).
Slew rates less than 1.0V/ns require the timing parameters
to be derated as specified.
the SSTL_18 standard (i.e., the receiver will effectively
switch as a result of the signal crossing the AC input level
and will remain in that state as long as the signal does not
ring back above [below] the DC input LOW [HIGH] level).
Command/Address input timing must be derated if the slew
rate is not 1.0V/ns. This is easily accommodated using tISb
and the Setup and Hold Time Derating Values table. tIS
timing (tISb) is referenced from VIH (AC) for a rising signal
and VIL(AC) for a falling signal. tIH timing (tIHb) is
referenced from VIH(AC) for a rising signal and VIL(DC)
for a falling signal. The timing table also lists the tISb and
tIHb values for a 1.0V/ns slew rate; these are the “base”
values.
timing must be derated if the slew rate is not 1.0V/ns. This
is easily accommodated if the timing is referenced from
the logic trip points. tDS timing (tDSb) is referenced from
VIH (AC) for a rising signal and VIL (AC) for a falling signal.
tIH timing (tIHb) is referenced from VIH(DC) for a rising
signal and VIL(DC) for a falling signal. The timing table
lists the tDSb and tDHb values for a 1.0V/ns slew rate. If
the DQS, /DQS differential strobe feature is not enabled,
timing is no longer referenced to the crosspoint of DQS, /
DQS. Data timing is now referenced to VREF, provided the
DQS slew rate is not less than 1.0V/ns. If the DQS slew
rate is less than 1.0V/ns, then data timing is now referenced
to VIH(AC) for a rising DQS and VIL(DC) for a falling DQS.
Output (VOUT)
VTT=VDDQ/2
25 Ω
Reference Point
Document Part Number 61000-02973-106 July 2007 Page 13
17. The data valid window is derived by achieving other
10. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX)
11. The intent of the Don’t Care state after completion of the
12. This is not a device limit. The device will operate with a
13. It is recommended that DQS be valid (HIGH or LOW) on or
14. The refresh period is 64ms. This equates to an average
15. Each byte lane has a corresponding DQS.
16. CK and /CK input slew rate must be ≥ 1V/ns (≥ 2 V/ns if
18. tJIT specification is currently TBD.
19. MIN(tCL, tCH) refers to the smaller of the actual clock low
20. tHP (MIN) is the lesser of tCL minimum and tCH minimum
8. tHZ and tLZ transitions occur in the same access time
9. This maximum value is derived from the referenced test
windows as valid data transitions. These parameters are
not referenced to a specific voltage level, but specify when
the device output is no longer driving (tHZ) or begins driving
(tLZ).
load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST
(MAX) condition.
condition.
postamble is the DQS-driven signal should either be high,
low or High-Z and that any signal transition within the input
switching region must follow valid input requirements. That
is if DQS transitions high (above VIHDC(min) then it must
not transition low (below VIH(DC) prior to tDQSH(min).
negative value, but system performance could be degraded
due to bus turnaround.
before the WRITE command. The case shown (DQS going
from High-Z to logic LOW) applies when no WRITEs were
previously in progress on the bus. If a previous WRITE
was in progress, DQS could be HIGH during this time,
depending on tDQSS.
refresh rate of 7.8125µs. However, a REFRESH command
must be asserted at least once every 70.3µs or tRFC
(MAX). To ensure all rows of all banks are properly
refreshed, 8192 REFRESH commands must be issued
every 64ms.
measured differentially).
specifications - tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP
- tQHS). The data valid window derates in direct proportion
to the clock duty cycle and a practical data valid window
can be derived.
time and the actual clock high time as provided to the device
(i.e. This value can be greater than the minimum
specification limits for tCL and tCH). For example, tCL and
tCH are = 50 percent of the period, less the half period
jitter [tJIT(HP)] of the clock source, and less the half period
jitter due to cross talk [tJIT(cross talk)] into the clock traces.
actually applied to the device CK and /CK inputs.
240-PIN RDIMM
(Notes continued on next page)