SL72P4M128M8M-B05AYU STEC, SL72P4M128M8M-B05AYU Datasheet - Page 15

• Manufacturer Part Number: SL72P4M128M8M-B05AYU
• Manufacturer: STEC

Specifications of SL72P4M128M8M-B05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 9Gb
• Access Time (max): 600ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 4.77A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P4M128M8M-B05AY(W)U
REGISTER ELECTRICAL CHARACTERISTICS
0°C≤TOPR≤+70°C; VDD=VDDQ=+2.5V ±0.2V; Unless otherwise stated
REGISTER TIMING REQUIREMENTS
Over recommended operating free-air temperature range, unless otherwise noted; VDD=+1.8V ±0.1V
REGISTER SWITCHING CHARACTERISTICS
Over recommended operating free-air temperature range, unless otherwise noted; VDD=+1.8V ±0.1V
Symbol
VIK
VOH
VOL
II
IDD
IDDD
rOH
rOL
rO(D)
Ci
(per each data input)
Dynamic Operating
Dynamic operating
Operating (Static)
[rOH - rOL] each
Standby (Static)
CLK and /CLK
Parameters
Output High
Output Low
separate bit
Data Inputs
(clock only)
All Inputs
1. Guaranteed by design, not 100% tested in production.
2. For data signal input slew rate of 1V/ns.
3. For data signal input slew rate of 0.5V/ns and < 1V/ns.
4. CLK, /CLK signal input slew rate of 1V/ns.
Symbol
/RESET
fclock
Th
tS
Clock frequency
Parameters
Setup time
Hold time, fast slew rate
Hold time, slow slew rate
tPDMSS
1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
Symbol
tPDM
fmax
tphl
Conditions
II = -18mA
IOH = -100µA
IOH = -16mA
IOL = 100µA
IOL = 16mA
VI = VDD or GND
0.01
/RESET = GND, IO = 0
VI = VIH(AC) or VIL(AC),
/RESET = VDD, IO = 0,
VI = VIH(AC) or VIL(AC),
CLK and /CLK switching
50% duty cycle.
VI = VIH(AC) or VIL (AC),
CLK and CLK# switching
50% duty cycle. One data
input switching at half clock
IOH = -20m
IOL = 20mA
IO = 20mA, TA = 25° C
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
VI = VDDQ or GND
/RESET = VDD, IO = 0
/RESET = VDD, IO = 0
1
2
From (Input)
CLK, /CLK
CLK, /CLK
/RESET
2,4
3,4
,
Data before CLK ↑, /CLK ↓
Data before CLK ↑, /CLK ↓
Data after CLK ↑, /CLK ↓
Data after CLK ↑, /CLK ↓
To (Output)
Document Part Number 61000-02973-106 July 2007 Page 15
Q
Q
Q
1.7V - 1.9V
1.7V - 1.9V
VDDQ
1.7V
1.7V
1.9V
1.9V
1.9V
1.8V
1.8V
µA
1.41
Min
270
Typ Max Units
VDDQ - 0.2
1.75
1.95
Min
2.5
0.75
0.50
0.70
3
Min
2
0.9
MHz
ns
ns
240-PIN RDIMM
Max
300
TBD
TBD
TBD
Typ
2.5
Units
MHz
ns
ns
ns
ns
Max
0.35
0.01
-1.2
0.2
3.5
±5
4
3
MHz/data
µA/clock
µ/clock
Units
MHz
mA
µA
pF
pF
pF
Ω
Ω
Ω
V
V
V
V