PPC405GPR-3BB400 Applied Micro Circuits Corporation, PPC405GPR-3BB400 Datasheet - Page 50

• Manufacturer Part Number: PPC405GPR-3BB400
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GPR-3BB400

• Family Name: 405GPr
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/1.85V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7/1.8V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / Rohs Status: Not Compliant

405GPr – Power PC 405GPr Embedded Processor
I/O Specifications—Group 2
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GPr package pin. System designers must use the PPC405GPr
4. PerClk timing is specified with a 10pF load at the package pin. The indicated timing is valid only if PerClk feedback is
5. Input timings are specified at 1.5V, assuming transition times between 1 and 2ns, when measured between the 10% and
6. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
50
SDRAM Interface
BA1:0
BankSel3:0
CAS
ClkEn0:1
DQM0:3
DQMCB
ECC0:7
MemAddr12:0
MemData0:31
RAS
WE
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr0:31
PerBLast
PerCS0
PerCS1:7[GPIO10:16]
PerData0:31
PerOE
PerPar0:3
PerR/W
PerReady
PerWBE0:3
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
PerErr
command is used by SDRAM.
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
selected. Refer to the PowerPC 405GPr Embedded Processor User’s Manual for more information.
90% points of the output voltage.
Signal
Setup Time
(T
IS
1.4
1.4
3.2
2.2
3.3
4.7
2.3
3.3
5.5
2.3
4.1
2.1
3.1
2.4
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
dc
min)
Input (ns)
Hold Time
(T
IH
0.9
na
na
na
na
na
na
na
na
na
na
dc
na
na
na
na
na
na
na
0
0
0
0
0
0
0
0
0
0
0
0
0
min)
Valid Delay
(T
OV
4.5
4.5
4.4
3.9
4.5
4.3
4.5
4.6
5.1
4.4
4.4
6.1
6.4
7.1
6.5
6.5
7.2
6.5
7.2
6.6
6.1
6.1
5.9
6.1
0.7
na
na
na
na
na
na
6
max)
Output (ns)
Hold Time
(T
OH
-0.5
1.6
1.5
1.5
1.4
1.4
1.4
1.5
1.5
1.4
1.5
1.5
2.2
2.3
2.1
1.9
2.1
2.1
2.1
2.2
2.2
2.1
na
na
na
na
na
na
2
2
1
2
min)
(minimum)
Output Current (mA)
I/O H
15.3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
10.3
10.3
15.3
10.3
10.3
15.3
10.3
15.3
10.3
10.3
10.3
10.3
15.3
10.3
15.3
23
na
na
na
na
na
na
Revision 2.05 – March 24, 2008
(minimum)
I/O L
10.2
10.2
10.2
19.3
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
na
na
na
na
na
na
Data Sheet
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
SysClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
Clock
Notes
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
2, 5
2, 5
2, 5
2, 5
2, 5
2, 5
4, 5
5
5
5
5
5
5
5
5
5
AMCC
5
5
5
5
5
5
5
5
5
5
5