MT48LC2M32B2P-7:GTR Micron Technology Inc, MT48LC2M32B2P-7:GTR Datasheet - Page 33

• Manufacturer Part Number: MT48LC2M32B2P-7:GTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC2M32B2P-7:GTR

• Lead Free Status / Rohs Status: Compliant

Power-Down
Figure 22:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Terminating a WRITE Burst
Note:
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress (see Figure 24 on page 34). If power-down
occurs when all banks are idle, this mode is referred to as precharge power-down; if
power-down occurs when there is a row active in either bank, this mode is referred to as
active power-down. Entering power-down deactivates the input and output buffers,
excluding CKE, for maximum power savings while in standby. The device may not
remain in the power-down state longer than the refresh period (
refresh operations are performed in this mode.
The power-down state is exited by registering an NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
ADDRESS
DQMs are LOW.
CLK
DQ
BANK,
WRITE
COL n
D
T0
n
IN
TERMINATE
BURST
T1
DON’T CARE
COMMAND
(ADDRESS)
(DATA)
T2
NEXT
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CKS).
©2001 Micron Technology, Inc. All rights reserved.
t
64Mb: x32 SDRAM
REF or
t
REF
Commands
AT
) since no