MT48LC2M32B2P-7:GTR Micron Technology Inc, MT48LC2M32B2P-7:GTR Datasheet - Page 67

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MT48LC2M32B2P-7:GTR

Manufacturer Part Number
MT48LC2M32B2P-7:GTR
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48LC2M32B2P-7:GTR

Lead Free Status / Rohs Status
Compliant
Figure 49:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
COMMAND
BA0, BA1
DQM 0-3
A0-A9
WRITE – DQM Operation
CKE
A10
CLK
DQ
Notes:
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
1. For this example, BL = 4.
2. A8 and A9 = “Don’t Care.”
t RCD
t CK
T1
NOP
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
t DS
WRITE
T2
BANK
D
IN
t CMH
t DH
t CH
m
T3
NOP
67
t DS
D
T4
IN
NOP
m + 2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t DS
D
T5
IN
NOP
m + 3
t DH
NOP
T6
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Timing Diagrams
NOP
DON’T CARE
UNDEFINED
T7

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