MT48LC16M16A2P-75:DTR Micron Technology Inc, MT48LC16M16A2P-75:DTR Datasheet - Page 5

• Manufacturer Part Number: MT48LC16M16A2P-75:DTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16A2P-75:DTR

• Lead Free Status / Rohs Status: Compliant

256Mb: x4, x8, x16 SDRAM
List of Figures
Figure 1: 64 Meg x 4 Functional Block Diagram ................................................................................................ 8
Figure 2: 32 Meg x 8 Functional Block Diagram ................................................................................................ 9
Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 10
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11
Figure 5: 60-Ball FBGA (Top View) ................................................................................................................. 12
Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13
Figure 7: 54-Pin Plastic TSOP (400 mil) ........................................................................................................... 15
Figure 8: 60-Ball FBGA "FB" (8mm x 16mm) (x4, x8) ....................................................................................... 16
Figure 9: 54-Ball VFBGA "FG" (8mm x 14mm) (x16) ........................................................................................ 17
Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) .............................................. 19
Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ........................................... 20
Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) ............................................. 20
Figure 13: ACTIVE Command ........................................................................................................................ 32
Figure 14: READ Command ........................................................................................................................... 33
Figure 15: WRITE Command ......................................................................................................................... 34
Figure 16: PRECHARGE Command ................................................................................................................ 35
Figure 17: Initialize and Load Mode Register .................................................................................................. 44
Figure 18: Mode Register Definition ............................................................................................................... 46
Figure 19: CAS Latency .................................................................................................................................. 49
t
t
t
Figure 20: Example: Meeting
RCD (MIN) When 2 <
RCD (MIN)/
CK < 3 ......................................................... 50
Figure 21: Consecutive READ Bursts .............................................................................................................. 52
Figure 22: Random READ Accesses ................................................................................................................ 53
Figure 23: READ-to-WRITE ............................................................................................................................ 54
Figure 24: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 55
Figure 25: READ-to-PRECHARGE .................................................................................................................. 55
Figure 26: Terminating a READ Burst ............................................................................................................. 56
Figure 27: Alternating Bank Read Accesses ..................................................................................................... 57
Figure 28: READ Continuous Page Burst ........................................................................................................ 58
Figure 29: READ – DQM Operation ................................................................................................................ 59
Figure 30: WRITE Burst ................................................................................................................................. 60
Figure 31: WRITE-to-WRITE .......................................................................................................................... 61
Figure 32: Random WRITE Cycles .................................................................................................................. 62
Figure 33: WRITE-to-READ ............................................................................................................................ 62
Figure 34: WRITE-to-PRECHARGE ................................................................................................................. 63
Figure 35: Terminating a WRITE Burst ........................................................................................................... 64
Figure 36: Alternating Bank Write Accesses .................................................................................................... 65
Figure 37: WRITE – Continuous Page Burst .................................................................................................... 66
Figure 38: WRITE – DQM Operation ............................................................................................................... 67
Figure 39: READ With Auto Precharge Interrupted by a READ ......................................................................... 69
Figure 40: READ With Auto Precharge Interrupted by a WRITE ....................................................................... 70
Figure 41: READ With Auto Precharge ............................................................................................................ 71
Figure 42: READ Without Auto Precharge ....................................................................................................... 72
Figure 43: Single READ With Auto Precharge .................................................................................................. 73
Figure 44: Single READ Without Auto Precharge ............................................................................................. 74
Figure 45: WRITE With Auto Precharge Interrupted by a READ ....................................................................... 75
Figure 46: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 75
Figure 47: WRITE With Auto Precharge .......................................................................................................... 76
Figure 48: WRITE Without Auto Precharge ..................................................................................................... 77
Figure 49: Single WRITE With Auto Precharge ................................................................................................ 78
Figure 50: Single WRITE Without Auto Precharge ........................................................................................... 79
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256Mb_sdr.pdf - Rev. N 1/10 EN
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