SAK-C167CS-L33M Infineon Technologies, SAK-C167CS-L33M Datasheet - Page 69
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SAK-C167CS-L33M
Manufacturer Part Number
SAK-C167CS-L33M
Description
Manufacturer
Infineon Technologies
Datasheet
1.SAK-C167CS-L33M.pdf
(81 pages)
Specifications of SAK-C167CS-L33M
Cpu Family
C166
Device Core Size
16b
Frequency (max)
33MHz
Interface Type
CAN/SPI/USART
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
11KB
# I/os (max)
111
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
24-chx10-bit
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
MQFP
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAK-C167CS-L33M
Manufacturer:
HITACHI
Quantity:
6 220
Company:
Part Number:
SAK-C167CS-L33M CA+
Manufacturer:
Infineon Technologies
Quantity:
10 000
The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a given
device, however, this bandwidth is smaller than the specified range. This is also due to
interdependencies between certain parameters. Some of these interdependencies are
described as relative timing (see below) or in additional notes (see standard timing).
Table 18
Parameter
Output hold time after WR rising edge
Valid for: address, write data out
Input hold time after RD rising edge
Valid for: read data in
1)
2)
General Notes For The Following Bus Timing Figures
These standard notes apply to all subsequent timing figures. Additional individual notes
are placed at the respective figure.
1)
2)
3)
4)
Data Sheet
Not 100% tested, guaranteed by design and characterization.
See also note
The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay feature
(bit BUSCON.RWDCx).
The rising edge of signal WR/WRH/WRL/WrCS is controlled by the early write feature (bit BUSCON.EWENx).
A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive.
A bus cycle is extended here, if an MTTC waitstate is selected.
3)
External Bus Relative Timing (Operating Conditions apply)
in
Table
17.
2)
65
Symbol
t
t
50
51
CC 0
SR –
min.
Limits
max.
–
0
C167CS-4R
V2.2, 2001-08
1)
C167CS-L
Unit
ns
ns