LH28F800BVE-BTL90 Sharp Electronics, LH28F800BVE-BTL90 Datasheet - Page 15
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LH28F800BVE-BTL90
Manufacturer Part Number
LH28F800BVE-BTL90
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F800BVE-BTL90.pdf
(42 pages)
Specifications of LH28F800BVE-BTL90
Cell Type
NOR
Density
8Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
20/19Bit
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH28F800BVE-BTL90
Manufacturer:
SHARP
Quantity:
103
Part Number:
LH28F800BVE-BTL90
Manufacturer:
SHARP
Quantity:
20 000
4.6 Word/Byte Write Command
Word/byte write is executed by a two-cycle command
sequence. Word/byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
Reliable
V
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V
to "1". Successful word/byte write for boot blocks requires
that the corresponding if set, that WP#=V
If word/byte write is attempted to boot block when the
corresponding WP#=V
be set to "1". Word/byte write operations with
V
attempted.
sharp
CC
PP
IH
<RP#<V
≤V
=2.7V-3.6V and V
PPLK
word/byte writes can only occur when
, status register bits SR.3 and SR.4 will be set
HH
produce spurious results and should not be
IL
PP
or RP#=V
=V
PPH1/2
. In the absence of this
IH
, SR.1 and SR.4 will
IH
or RP#=V
HH
LHF80V11
.
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests that
the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1").
RY/BY# will also transition to High Z. Specification
t
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.8), a word/byte write operation can also be
suspended. During a word/byte write operation with block
erase suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to V
SR.6 will remain "1" to indicate block erase suspend
status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear and RY/BY# will return to V
the Erase Resume command is written, the device
automatically outputs status register data when read (see
Figure 7). V
level used for block erase) while block erase is suspended.
RP# must also remain at V
used for block erase). WP# must also remain at V
(the same WP# level used for block erase). Block erase
cannot resume until word/byte write operations initiated
during block erase suspend have completed.
WHRZ2
defines the block erase suspend latency.
PP
must remain at V
IH
or V
HH
PPH1/2
(the same RP# level
(the same V
OL
. However,
OL
IL
Rev. 1.1
. After
or V
13
PP
IH