LH28F800BVE-BTL90 Sharp Electronics, LH28F800BVE-BTL90 Datasheet - Page 5

• Manufacturer Part Number: LH28F800BVE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F800BVE-BTL90

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

1 INTRODUCTION
This datasheet contains LH28F800BVE-BTL90
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F800BVE-BTL90 Smart3
Flash memory are:
Please note following important differences:
1.2 Product Overview
The LH28F800BVE-BTL90 is a high-performance 8M-bit
Smart3 Flash memory organized as 1M-byte of 8 bits or
512K-word of 16 bits. The 1M-byte/512K-word of data is
arranged in two 8K-byte/4K-word boot blocks, six 8K-
byte/4K-word parameter blocks and fifteen 64K-byte/32K-
word main blocks which are individually erasable in-
system. The memory map is shown in Figure 3.
Smart3 technology provides a choice of V
combinations, as shown in Table 1, to meet system
performance and power expectations. V
eliminates the need for a separate 12V converter, while
sharp
•Smart3 Technology
•Enhanced Suspend Capabilities
•Boot Block Architecture
•V
•To take advantage of Smart3 technology, allow V
block erase and word/byte write operations. The V
voltage transitions to GND is recommended for
designs that switch V
and V
PPLK
PP
has been lowered to 1.5V to support 2.7V-3.6V
connection to 2.7V-3.6V.
PP
off during read operation.
PP
at 2.7V-3.6V
CC
and V
CC
LHF80V11
PP
PP
V
performance. In addition to flexible erase and program
voltages, the dedicated V
protection when V
Internal V
configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and word/byte write
operations.
A block erase operation erases one of the device’s 32K-
word blocks typically within 0.51s (2.7V-3.6V V
11.4V-12.6V V
(2.7V-3.6V V
blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software
to suspend block erase to read or write data from any other
block.
Writing memory data is performed in
increments of the device’s 32K-word blocks typically
within 12.6µs (2.7V-3.6V V
word blocks typically within 24.5µs (2.7V-3.6V V
11.4V-12.6V V
enables the system to read data or execute code from any
other flash memory array location.
Table 1. V
PP
=12V maximizes block erase and word/byte write
V
2.7V-3.6V
CC
CC
Voltage
CC
CC
and V
and V
PP
, 11.4V-12.6V V
PP
), 4K-word blocks typically within 0.31s
PP
).
Smart3 Technology
≤V
PP
PP
Word/byte write suspend mode
PPLK
Voltage Combinations Offered by
detection Circuitry automatically
PP
.
2.7V-3.6V, 11.4V-12.6V
CC
pin gives complete data
, 11.4V-12.6V V
PP
V
) independent of other
PP
Voltage
word/byte
PP
Rev. 1.1
), 4K-
CC
CC
3
,
,