AM29LV640MB110REI Spansion Inc., AM29LV640MB110REI Datasheet - Page 35

• Manufacturer Part Number: AM29LV640MB110REI
• Manufacturer: Spansion Inc.

Specifications of AM29LV640MB110REI

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

The system must write the Program Resume com-
mand (address bits are don’t care) to exit the Program
Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables
13
chip erase command sequence. Note that the autose-
lect and CFI functions are unavailable when an erase
operation is in progress.
February 1, 2007 26190C8
No
Figure 6. Program Suspend/Program Resume
shows the address and data requirements for the
Sequence in Progress
Program Operation
Write address/data
Write address/data
Program Suspend
or Write-to-Buffer
Device reverts to
operation prior to
Read data as
Wait 15 μs
XXXh/B0h
XXXh/30h
reading?
required
Done
Yes
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Write Program Resume
Command Sequence
D A T A
12
Am29LV640MT/B
and
S H E E T
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
See
on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 7
tion. See the table,
page 48
ure 19
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Tables
the address and data requirements for the sector
erase command sequence. Note that the autoselect
and CFI functions are unavailable when an erase op-
eration is in progress.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands can be written. Loading the sector erase buffer
can be done in any sequence, and the number of sec-
tors can be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise erasure can begin. Any sector erase ad-
dress and command following the exceeded time-out
might or might not be accepted. It is recommended
that processor interrupts be disabled during this time
to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase com-
mand is written. Any command other than Sector
Erase or Erase Suspend during the time-out pe-
riod resets the device to the read mode. The sys-
tem must rewrite the command sequence and any
additional addresses and commands.
Write Operation Status on page 38
for timing diagrams.
in
illustrates the algorithm for the erase opera-
AC Characteristics
Erase and Program Operations on
for parameters, and
12
and
for information
13
shows
Fig-
33