AM29LV640MB110REI Spansion Inc., AM29LV640MB110REI Datasheet - Page 42

• Manufacturer Part Number: AM29LV640MB110REI
• Manufacturer: Spansion Inc.

Specifications of AM29LV640MB110REI

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

40
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit can stop toggling as DQ5
changes to “1.” See
for more information.
No
Figure 9. Toggle Bit Algorithm
Reset Command
Complete, Write
Read DQ7–DQ0
Read DQ7–DQ0
Read DQ7–DQ0
Program/Erase
Operation Not
Toggle Bit
Toggle Bit
DQ5 = 1?
= Toggle?
= Toggle?
START
Twice
DQ6: Toggle Bit I
Yes
Yes
Yes
Operation Complete
No
No
and
Program/Erase
DQ2: Toggle Bit II
D A T A
Am29LV640MT/B
S H E E T
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system can use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to
puts for DQ2 and DQ6.
Figure 9
form, and
algor ithm. See also
page
gram.
and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high.
(See
should then determine again whether the toggle bit is
toggling, since the toggle bit might have stopped tog-
gling just as DQ5 went high. If the toggle bit is no
longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to re-
turn to reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system can continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it can choose to perform
DQ2: Toggle Bit II on page
39.
Figure 22
Figure 9
shows the toggle bit algorithm in flowchart
Figure 21
DQ2: Toggle Bit II on page 40
shows the differences between DQ2
for the following discussion. When-
shows the toggle bit timing dia-
RY/BY#: Ready/Busy# on
Table 14
26190C8 February 1, 2007
40.) If it is, the system
to compare out-
explains the