LH28F400SUE-NC80 Sharp Electronics, LH28F400SUE-NC80 Datasheet - Page 5

• Manufacturer Part Number: LH28F400SUE-NC80
• Manufacturer: Sharp Electronics

Specifications of LH28F400SUE-NC80

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

4M (512K × 8, 256K × 16) Flash Memory
INTRODUCTION
revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and
communication products. With innovative capabilities,
5 V single voltage operation and very high read/write
performance, the LH28F400SU-NC is also the ideal
choice for designing embedded mass storage flash
memory systems.
symmetrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsimile, game, PC, printer and handy terminal. The
LH28F400SU-NC’s single power supply operation en-
ables the design of memory cards which can be read/
written in 5.0 V systems. Its x8/x16 architecture allows
the optimization of memory to processor interface. The
flexible block locking option enables bundling of execut-
able application software in a Resident Flash Array or
memory card. Manufactured on Sharp’s 0.45 µm
ETOX™ process technology, the LH28F400SU-NC is
the most cost-effective, high-density 5.0 V flash memory.
DESCRIPTION
(4,194,304) block erasable non-volatile random access
memory organized as either 256K × 16 or 512K × 8.
The LH28F400SU-NC includes thirty-two 16K (16,384)
blocks. A chip memory map is shown in Figure 5.
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
LH28F400SU-NC:
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•
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•
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tem interface between the microprocessor or
microcontroller and the internal memory operation.
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash Memory.
Sharp’s LH28F400SU-NC 4M Flash Memory is a
The LH28F400SU-NC’s independently lockable 32
The LH28F400SU-NC is a high performance 4M
The implementation of a new architecture, with many
Among the significant enhancements of the
5 V Read, Write/Erase Operation (5 V V
Low Power Capability
Improved Write Performance
Dedicated Block Write/Erase Protection
Command-Controlled Memory Protection
Set/Reset Capability
A Command User Interface (CUI) serves as the sys-
Internal Algorithm Automation allows Byte Writes and
CC
, V
PP
)
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
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13 µs per byte or within 20 µs per word. A Block Erase
operation erases one of the 32 blocks in typically 0.6
seconds, independent of the other blocks.
It is desirable in case of which you have to implement
Erase operation maximum 32 times.
Two-Byte Serial Write which is operated by three times
command input. Writing of memory data is performed
typically within 20 µs per two-byte. This feature can im-
prove 8-bit system write performance by up to typically
10 µs per byte.
commands to the device. Status Register (described in
detail later) and a RY
tion on the progress of the requested operation.
requires an operation to complete before the next
operation can be requested, also it allows to suspend
block erase to read data from any other block, and
allow to resume erase operation.
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or Ap-
plication Code. Each block has an associated non-vola-
tile lock-bit which determines the lock status of the block.
In addition, the LH28F400SU-NC has a software con-
trolled master Write Protect circuit which prevents any
modifications to memory blocks whose lock-bits are set.
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP
locked Blocks can be used. If used, Erase is performed
with reflecting actual lock status, and after that Write
and Block Erase can be used.
A Superset of commands have been added to the
Software Locking of Memory Blocks
Memory Protection Set/Reset Capability
Two-Byte Serial Writes in 8-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed typically within
LH28F400SU-NC allows to erase all unlocked blocks.
Only in x8 mode, LH28F400SU-NC enables
All operations are started by a sequence of Write
Same as the LH28F008SA, LH28F400SU-NC
The LH28F400SU-NC provides user-selectable block
When the device power-up or RP
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/ BY
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output pin provide informa-
»
turns High, Erase All Un-
»
LH28F400SU-NC
turns High, Write
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