LH28F008SCT-V12 Sharp Electronics, LH28F008SCT-V12 Datasheet - Page 13

• Manufacturer Part Number: LH28F008SCT-V12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCT-V12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V
V
high voltage, block contents are protected against
erasure. If block erase is attempted while V
V
block erase requires that the corresponding block
lock-bit be cleared or, if set, that RP# = V
block erase is attempted when the corresponding
block lock-bit is set and RP# = V
will be set to "1". Block erase operations with V
RP# < V
not be attempted.
4.6 Byte Write Command
Byte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the byte write and write verify algorithms
internally. After the byte write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the byte write event by analyzing the
RY/BY# pin or status register bit SR.7.
CC1/2
PPLK
, SR.3 and SR.5 will be set to "1". Successful
and V
HH
produce spurious results and should
PP
= V
PPH1/2
. In the absence of this
IH
, SR.1 and SR.5
HH
CC
PP
IH
. If
=
<
≤
- 13 -
When byte write is complete, status register bit
SR.4 should be checked. If byte write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.
Reliable byte writes can only occur when V
V
high voltage, memory contents are protected
against byte writes. If byte write is attempted while
V
be set to "1". Successful byte write requires that the
corresponding block lock-bit be cleared or, if set,
that RP# = V
corresponding block lock-bit is set and RP# = V
SR.1 and SR.4 will be set to "1". Byte write
operations with V
results and should not be attempted.
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or byte write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V
Specification t
suspend latency.
At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Byte Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Byte
CC1/2
PP
≤ V
and V
PPLK
, status register bits SR.3 and SR.4 will
HH
PP
. If byte write is attempted when the
WHRH2
= V
IH <
PPH1/2
RP# < V
defines the block erase
LH28F008SC-V/SCH-V
. In the absence of this
HH
produce spurious
CC
OH
IH
=
,
.